Data Sheet
FEATURES
9 GHz to 10 GHz,
X-Band, GaAs, MMIC, Low Noise Converter
HMC8108
FUNCTIONAL BLOCK DIAGRAM
32
LNA_VD1
30
LNA_VD2
28
IF_Q
26
GND
31
NIC
29
NIC
27
NIC
25
NIC
24
23
22
21
20
19
Conversion gain: 13 dB typical
Image rejection: 20 dBc typical
Noise figure: 2 dB typical
Input power for 1 dB compression: −4 dBm typical
Input third-order intercept: 6 dBm typical
Output saturated power: 10 dBm typical
LO leakage at the IF port: −20 dBm typical
LO leakage at the RF port: −37 dBm typical
32-terminal, 5 mm × 5 mm, ceramic leadless chip carrier (LCC)
NIC
NIC
LNA_VG1
NIC
RFIN
NIC
VCTRL
NIC
1
2
3
4
5
6
7
8
NIC
BUFF_VD
NIC
NIC
LOIN
NIC
NIC
NIC
APPLICATIONS
Point to point and point to multipoint radios
Military radar
Satellite communications
HMC8108
NIC
11
LNA_VG2
10
IF_I
13
18
17
9
NIC
14
MIX_VG
15
BUFF_VG
16
NIC
12
NIC
EPAD
15133-001
Figure 1.
GENERAL DESCRIPTION
The
HMC8108
is a compact, X-band, gallium arsenide (GaAs),
monolithic microwave integrated circuit (MMIC) in-phase/
quadrature (I/Q), low noise converter in a ceramic, leadless chip
carrier, RoHS compliant package. The
HMC8108
converts radio
frequency (RF) input signals ranging from 9 GHz to 10 GHz to a
typical single-ended intermediate frequency (IF) signal of 60 MHz
at its output. This device provides a small signal conversion gain
of 13 dB with a noise figure of 2 dB and image rejection of 20 dBc.
The
HMC8108
uses a low noise amplifier followed by an image
reject mixer that is driven by an active LO buffer amplifier. The
image reject mixer eliminates the need for a filter following the
low noise amplifier and removes thermal noise at the image
frequency. I/Q mixer outputs are provided, and an external 90°
hybrid is needed to select the required sideband. The
HMC8108
is a much smaller alternative to hybrid style, image reject mixer,
downconverter assemblies and is compatible with surface-mount
manufacturing techniques.
Rev. 0
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HMC8108
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Data Sheet
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 15
Biasing Sequence ........................................................................ 15
Results .......................................................................................... 15
Evaluation Board Information ................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
2/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 18
Data Sheet
SPECIFICATIONS
HMC8108
T
A
= −25°C, IF = 60 MHz, LNA_VD1/LNA_VD2 = +3 V, BUFF_VD = +3 V, VCTRL = −1 V, MIX_VG = −1.4 V, LO power= −5 dBm,
downconverter mode with lower side selected and external 90° hybrid at the IF ports, unless otherwise noted.
Table 1.
Parameter
OPERATING CONDITIONS
Frequency Range
Radio Frequency
Local Oscillator
Intermediate Frequency
LO Input Level
PERFORMANCE
Conversion Gain
Gain Variation Range
Noise Figure
Image Rejection
Input Power for 1 dB Compression
Input Third-Order Intercept
Input Second-Order Intercept
Output Saturated Power
LO Leakage at the IF Port
1
LO Leakage at the RF Port
RF Leakage at the IF Port
1
Amplitude Balance
1
Phase Balance
1
Return Loss
RF Port
LO Port
IF Port
1
POWER SUPPLY
LNA_VD1
LNA_VD2
BUFF_VD
1
Symbol
Min
Typ
Max
Unit
RF
LO
IF
9
9
0.02
−10
10
10
13
15
2
20
−4
6
12
10
−20
−37
−27
3
4
15
9
20
20
30
40
10
10
1
0
GHz
GHz
GHz
dBm
dB
dB
dB
dBc
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Degree
dB
dB
dB
mA
mA
mA
NF
15
P1dB
IP3
IP2
P
SAT
2
2.5
−25
Measurements performed without external 90° hybrid at the IF ports.
Rev. 0 | Page 3 of 18
HMC8108
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Drain Bias Voltage
LNA_VD1
LNA_VD2
BUFF_VD
Gate Bias Voltage
LNA_VG1
LNA_VG2
MIX_VG
BUFF_VG
VCTRL
RF Input Power
LO Input Power
Maximum Peak Reflow Temperature (MSL3)
1
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Field Induced Charged Device Model (FICDM)
1
Data Sheet
THERMAL RESISTANCE
Rating
5.8 V
4.8 V
4.2 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
20 dBm
24 dBm
260°C
165°C
−40°C to +85°C
−65°C to 150°C
Class 0 (150 V)
Class C3 (250 V)
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3. Thermal Resistance
Package Type
E-32-1
1
1
θ
JA
93
θ
JC
119.47
Unit
°C/W
See JEDEC standard JESD51-2 for additional information on optimizing the
thermal impedance (PCB with 3 × 3 vias).
ESD CAUTION
See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 4 of 18
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LNA_VD1
NIC
LNA_VD2
NIC
IF_Q
NIC
GND
NIC
HMC8108
NIC
NIC
LNA_VG1
NIC
RFIN
NIC
VCTRL
NIC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
HMC8108
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
NIC
BUFF_VD
NIC
NIC
LOIN
NIC
NIC
NIC
9
10
11
12
13
14
15
16
NIC
LNA_VG2
NIC
NIC
IF_I
NIC
MIX_VG
BUFF_VG
EPAD
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 2, 4, 6, 8, 9, 11, 12,
14, 17 to 19, 21, 22,
24, 25, 27, 29, 31
3
5
7
10
13, 28
15
16
20
23
26
30
32
Mnemonic
NIC
LNA_VG1
RFIN
VCTRL
LNA_VG2
IF_I, IF_Q
MIX_VG
BUFF_VG
LOIN
BUFF_VD
GND
LNA_VD2
LNA_VD1
EPAD
Description
No Internal Connection. These pins are not connected internally.
Gate Bias Voltage for the First Low Noise Amplifier. See Figure 3 for the interface schematic.
Radio Frequency Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
Voltage Control. Gate bias attenuation control for the low noise amplifier. See Figure 5 for the interface
schematic.
Gate Bias Voltage for the Second Low Noise Amplifier. See Figure 6 for the interface schematic.
In-Phase and Quadrature Intermediate Frequency Output Pins. See Figure 7 for the interface schematic.
Gate Bias Voltage for FET Mixer. See Figure 8 for the interface schematic.
Gate Bias Voltage for the Local Oscillator Buffer. See Figure 9 for the interface schematic.
Local Oscillator Input. This pin is ac-coupled and matched to 50 Ω. See Figure 10 for the interface schematic.
Drain Bias Voltage for the Local Oscillator Buffer. See Figure 11 for the interface schematic.
Ground Connect. This pin must be connected to RF/dc ground. See Figure 12 for the interface schematic.
Drain Bias Voltage for the Second Low Noise Amplifier. See Figure 13 for the interface schematic.
Drain Bias Voltage for the First Low Noise Amplifier. See Figure 14 for the interface schematic.
Exposed Pad. Connect the exposed pad to RF/dc ground. See Figure 12 for the interface schematic.
Rev. 0 | Page 5 of 18
15133-002
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
