Data Sheet
FEATURES
Gain: 21 dB typical
Noise figure: 3.6 dB typical
Output power for 1 dB compression: 13 dBm typical
Input third-order intercept at maximum gain: 1 dBm typical
Output third-order intercept at maximum gain: 22 dBm typical
Saturated output power: 17 dBm typical
Input return loss: 15 dB typical
Output return loss: 17 dB typical
Die size: 2.844 mm × 0.999 mm × 0.05 mm
71 GHz to 86 GHz,
E-Band Low Noise Amplifier
HMC8325
GENERAL DESCRIPTION
The
HMC8325
is an integrated E-band gallium arsenide (GaAs),
monolithic microwave integrated circuit (MMIC), low noise
amplifier (LNA) chip that operates from 71 GHz to 86 GHz.
The
HMC8325
provides 21 dB of gain, 13 dBm of output P1dB,
22 dBm of OIP3, and 17 dBm of P
SAT
while requiring only 50 mA
from a 3 V power supply. The
HMC8325
exhibits excellent linearity
and is optimized for E-band communications and high capacity,
wireless backhaul radio systems. All data is taken with the chip
in a 50 Ω test fixture connected via a 3 mil wide × 0.5 mil thick ×
7 mil long ribbon on each port.
APPLICATIONS
E-band communication systems
High capacity wireless backhauls
Test and measurement
FUNCTIONAL BLOCK DIAGRAM
V
G1
4
5
6
V
D1
7
8
V
G2
9
10
V
D2
11
12
V
G3
13
14
V
D3
15
16
V
G4
17
18
V
D4
19
3
RF
IN
2
1
20
21
22
RF
OUT
HMC8325
Figure 1.
Rev. 0
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14692-001
HMC8325
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
Data Sheet
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 12
Application Information ................................................................ 13
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs ......................................................................................... 14
Handling Precautions ................................................................ 14
Mounting ..................................................................................... 14
Wire Bonding .............................................................................. 14
Assembly Diagram ..................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
SPECIFICATIONS
T
A
= 25°C, V
Dx
(V
D1
and V
D2
to V
D3
and V
D4
) = 3 V, unless otherwise noted.
Table 1.
Parameter
OPERATING CONDITIONS
Radio Frequency (RF) Range
PERFORMANCE
Gain
Gain Variation over Temperature
Output Power for 1 dB Compression (P1dB)
Saturated Output Power (P
SAT
)
Input Third-Order Intercept (IIP3) at Maximum Gain
1
Output Third-Order Intercept (OIP3) at Maximum Gain
1
Noise Figure
Return Loss
Input
Output
POWER SUPPLY
Total Drain Current (I
Dx
)
2
1
2
HMC8325
Min
71
19.5
Typ
Max
86
Unit
GHz
dB
dB/°C
dBm
dBm
dBm
dBm
dB
dB
dB
mA
21
0.02
13
17
1
22
3.6
15
17
50
4.5
Data taken at power output (P
OUT
) = 5 dBm/tone, 1 MHz spacing.
Adjust V
G1
and V
G2
to V
G3
and V
G4
from −2 V to 0 V to achieve a total drain current (I
Dx
) = 50 mA.
Rev. 0 | Page 3 of 16
HMC8325
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Drain Bias Voltage (V
D1
to V
D4
)
Gate Bias Voltage (V
G1
to V
G4
)
Maximum Junction Temperature (to
Maintain 1 Million Hours Mean Time to
Failure (MTTF))
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
Rating
4.5 V
−3 V to 0 V
175°C
−65°C to +150°C
−55°C to +85°C
Class 0 (150 V)
Data Sheet
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3. Thermal Resistance
Package Type
C-22-1
2
1
2
θ
JC1
225
Unit
°C/W
Based on ABLEBOND® 84-1LMIT as die attach epoxy.
Test Condition: Thermal impedance simulated values are based on
JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 4 of 16
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
4
V
G1
5
GND
6
V
D1
7
GND
8
V
G2
9
GND
10
V
D2
11
GND
12
V
G3
13
GND
14
V
D3
15
GND
16
V
G4
17
GND
18
V
D4
19
HMC8325
HMC8325
GND
RF
IN
GND
3
2
1
20
21
22
GND
RF
OUT
GND
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pad No.
1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22
2
5, 9, 13, 17
7, 11, 15, 19
21
Die Bottom
Mnemonic
GND
RF
IN
V
G1
to V
G4
V
D1
to V
D4
RF
OUT
GND
Description
Ground Connection.
RF Input. AC couple RF
IN
and match it to 50 Ω.
Gate Bias Voltage for the Low Noise Amplifier.
Drain Bias Voltage for the Low Noise Amplifier.
RF Output. AC couple RF
OUT
and match it to 50 Ω.
Ground. Die bottom must be connected to the RF/dc ground.
INTERFACE SCHEMATICS
14692-003
GND
V
D1
, V
D2
, V
D3
, V
D4
14692-006
Figure 3. GND Interface Schematic
14692-004
Figure 6. V
D1
to V
D4
Interface Schematic
RF
OUT
14692-007
RF
IN
Figure 4. RF
IN
Interface Schematic
Figure 7. RF
OUT
Interface Schematic
V
G1
, V
G2
, V
G3
, V
G4
Figure 5. V
G1
to V
G4
Interface Schematic
14692-005
Rev. 0 | Page 5 of 16
14692-002
