Data Sheet
FEATURES
Attenuation range: 1 dB LSB steps to 31 dB
Insertion loss: 6 dB typical at 33 GHz
Attenuation accuracy: ±0.5 dB
Input linearity
0.1 dB compression (P0.1dB): 24 dBm typical
3rd-order intercept (IP3): 40 dBm typical
Power handling: 27 dBm maximum
Dual-supply operation: ±5 V
CMOS-/TTL-compatible parallel control
24-lead, 4 mm × 4 mm LFCSP package
0.1 GHz to 33 GHz,1 dB LSB, 5-Bit,
GaAs Digital Attenuator
HMC939ATCPZ-EP
FUNCTIONAL BLOCK DIAGRAM
24
VSS
1
23
22
21
20
19
18
VDD
NIC
P0
P1
P2
P3
P4
NIC
2
17
NIC
NIC
NIC
3
DRIVER
4
2dB
4dB
8dB 16dB
16
15
NIC
NIC
RF1
5
14
13
7
8
9
10
11
12
RF2
NIC
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
NIC
6
NIC
NIC
NIC
NIC
NIC
NIC
PACKAGE
BASE
GND
16267-001
NIC = NO INTERNAL CONNECTION
Figure 1.
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems
GENERAL DESCRIPTION
The HMC939ATCPZ-EP is a 5-bit digital attenuator with a 31 dB
attenuation control range in 1 dB steps.
The HMC939ATCPZ-EP offers optimum insertion loss,
attenuation accuracy, and input linearity over the specified
frequency range from 100 MHz to 33 GHz.
The HMC939ATCPZ-EP requires dual-supply voltages,
V
DD
= 5 V and V
SS
= −5 V, and provides a complementary metal
oxide semiconductor (CMOS)-/transistor to transistor level
(TTL)-compatible parallel control interface by incorporating an
on-chip driver.
The HMC939ATCPZ-EP comes in a RoHS compliant, compact,
4 mm × 4 mm LFCSP package.
Additional application and technical information can be found
in the
HMC939ALP4E
data sheet.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC939ATCPZ-EP
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Data Sheet
Power Derating Curve ..................................................................4
ESD Caution...................................................................................4
Pin Configuration and Function Descriptions..............................5
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Outline Dimension............................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
10/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Data Sheet
SPECIFICATIONS
V
DD
= 5 V, V
SS
= −5 V, V
Px
= 0 V or V
DD
, T
CASE
= 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
INSERTION LOSS
Symbol
Test Conditions/Comments
0.1 GHz to 18 GHz
18 GHz to 26.5 GHz
26.5 GHz to 33 GHz
Between minimum and maximum
attenuation states, 0.1 GHz to 33 GHz
Between any successive attenuation
states, 0.1 GHz to 33 GHz
Between any successive attenuation
states, 0.1 GHz to 33 GHz
Referenced to insertion loss state
1 dB to 15 dB attenuation states,
0.1 GHz to 33 GHz
16 dB to 31 dB attenuation states,
0.1 GHz to 20 GHz
16 dB to 31 dB attenuation states,
20 GHz to 33 GHz
RF1 and RF2 pins, all attenuation
states, 0.1 GHz to 33 GHz
Between minimum and maximum
attenuation states
0.1 GHz to 18 GHz
18 GHz to 26.5 GHz
26.5 GHz to 33 GHz
Between all attenuation states
10% to 90% of radio frequency (RF)
output
50% digital control input voltage
(V
CTL
)
to 90% of RF output
All attenuation states
0.1 GHz to 0.5 GHz
0.5 GHz to 33 GHz
8 dBm per tone, 1 MHz spacing
0.1 GHz to 0.5 GHz
0.5 GHz to 33 GHz
Min
0.1
Typ
4.5
5.5
6
31
1
0.5
HMC939ATCPZ-EP
Max
33
5.5
7.0
8
Unit
GHz
dB
dB
dB
dB
dB
dB
ATTENUATION
Range
Step Size
Step Error
State Error
−(0.5 + 5% of
attenuation state)
−(0.5 + 5% of
attenuation state)
−(0.6 + 8% of
attenuation state)
10
+(0.5 + 5% of
attenuation state)
+(0.5 + 5% of
attenuation state)
+(0.6 + 8% of
attenuation state)
dB
dB
dB
dB
RETURN LOSS
RELATIVE PHASE
45
60
80
45
60
Degrees
Degrees
Degrees
ns
ns
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
INPUT LINEARITY
0.1 dB Compression
Third-Order Intercept
t
RISE
, t
FALL
t
ON
, t
OFF
P0.1dB
IP3
20
24
43
40
2.5
−7.0
4.5
−5.5
6.5
−3.0
dBm
dBm
dBm
dBm
mA
mA
SUPPLY CURRENT
Positive
Negative
DIGITAL CONTROL INPUTS
Voltage
Low
High
Current
Low and High
I
DD
I
SS
P0 to P4 pins
V
INL
V
INH
I
INL
, I
INH
0
2
<1
0.8
5
V
V
µA
Rev. 0 | Page 3 of 8
HMC939ATCPZ-EP
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Positive
Negative
Digital Control Input Voltage, V
CTL
RF Input Power (All Attenuation States,
f = 0.1 GHz to 33 GHz, T
CASE
= 85°C)
Continuous Power Dissipation, P
DISS
(T
CASE
= 85°C)
1
(T
CASE
= 105°C)
1
(T
CASE
= 125°C)
1
Temperature
Junction, T
J
Case, T
CASE
Storage
Reflow
2
Moisture Sensitivity Level 3
(MSL3) Rating
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
1
2
Data Sheet
THERMAL RESISTANCE
Rating
7V
−7 V
V
DD
+ 0.5 V
27 dBm
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JA
is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θ
JC
is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type
CP-24-22
1
1
0.453 W
0.314 W
0.174 W
150°C
−55°C to +125°C
−65°C to +150°C
260°C
θ
JA
213
θ
JC
143.5
2
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
2
The device is set to maximum attenuation state.
POWER DERATING CURVE
1.2
MAXIMUM POWER DISSIPATION (W)
1.0
250 V (Class 1A)
0.8
See Figure 2.
See the Ordering Guide for more information.
0.6
–40
–20
0
20
40
60
80
100
120
CASE TEMPERATURE (°C)
Only one absolute maximum rating can be applied at any one time.
Figure 2. Maximum Power Dissipation vs. Case Temperature (T
CASE
)
ESD CAUTION
Rev. 0 | Page 4 of 8
16267-002
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
0.4
0.2
0
–60
Data Sheet
NIC
HMC939ATCPZ-EP
P0
P1
P2
P3
P4
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
VSS
NIC
1
2
23
22
21
20
19
18
VDD
17
16
NIC
NIC
3
HMC939ATCPZ-EP
TOP VIEW
(Not to Scale)
NIC
NIC
4
15
NIC
RF1
5
14
13
7
NIC
RF2
NIC
NIC
6
8
NIC
9
NIC
10
NIC
11
NIC
12
NIC
PACKAGE
BASE
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2 to 4, 6 to 13,
15 to 17, 19
5, 14
18
20 to 24
Mnemonic
VSS
NIC
RF1, RF2
VDD
P4 to P0
EPAD
Description
Negative Supply Voltage.
Not Internally Connected. These pins are not internally connected; however, all data shown herein was
measured with these pins connected to the RF/dc ground of evaluation board.
RF Inputs or Outputs of Attenuator. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking
capacitor is necessary when the RF line potential is equal to 0 V dc.
Positive Supply Voltage.
Parallel Control Voltage Inputs. These pins select the required attenuation. There is no internal pull-up or
pull-down resistor on these pins; therefore, they must always be kept at a valid logic level (V
INH
or V
INL
) and
not be left floating.
Exposed Pad. The exposed pad must be connected to ground for proper operation.
Table 5. P4 to P0 Truth Table
P4
High
High
High
High
High
Low
Low
1
P3
High
High
High
High
Low
High
Low
Digital Control Input
1
P2
P1
High
High
High
High
High
Low
Low
High
High
High
High
High
Low
Low
P0
High
Low
High
High
High
High
Low
Attenuation
State (dB)
0 dB (reference)
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected.
Rev. 0 | Page 5 of 8
16267-003
GND
NOTES
1. NIC = NO INTERNAL CONNECTION
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
