IP101G
Preliminary Data Sheet
Single Port 10/100 MII/RMII/TP/Fiber
Fast Ethernet Transceiver
(85nm/Extreme Low PW, PWMT
®
and EMIMT
®
)
Features
10/100Mbps IEEE 802.3/802.3u compliant
Fast Ethernet transceiver
Supports 100Base-TX/FX Media Interface
Supports MII/ RMII Interface
Supports Auto MDI/MDIX function
Power Management Tool
- APS, auto power saving while Link-off
- 802.3az, protocol based power saving
- WOL+, light traffic power saving
- PWD, force-off power saving
- Supports MII with LPI for RX and TX
- Supports RMII with LPI for RX
Supports Base Line Wander compensation
Supports Interrupt function
Built in synchronization FIFO to support
jumbo frame size up to 12KB in MII mode (10KB
in RMII 100Mbps mode)
Supports MDC and MDIO to communicate
with the MAC
EMI Management Tool
- F/W based control
- 4 levels for mapping the difference layout
length on the PCB
Single 3.3V power supply
Built-in Vcore regulator
DSP-based PHY Transceiver technology
System Debug Assistant Tool
- 16 bit RX counter
- 9 bit RXError/CRC counter
- Isolate MII/RMII
- RX to TX Loopback
- Loopback MII/RMII
Using either 25MHz crystal/oscillator or
50MHz oscillator REF_CLK as clock source
Built-in 49.9ohm resistors for simplifying
BOM
Flexible LED display
Process: 85nm
General Description
Package and operation temperature
IP101G: dice, 0~70℃
IP101GA: 48LQFP, 0~70℃
IP101GR: 32QFN, 0~70℃
IP101GRI: 32QFN, -40~85℃
IP101G is an IEEE 802.3/802.3u compliant
single-port Fast Ethernet Transceiver for both
100Mbps and 10Mbps operations. It supports
Auto MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. To improve the system performance,
IP101G provides a hardware interrupt pin to
indicate the link, speed and duplex status
change. IP101G provides Media Independent
Interface (MII) or Reduced Media Independent
Interface (RMII) to connect with different types
of 10/100Mbps Media Access Controller (MAC).
IP101G is designed to use category 5
unshielded twisted-pair cable or Fiber-Optic
cables connecting to other LAN devices. A
PECL interface is supported to connect with an
external 100Base-FX fiber optical transceiver.
Except good performance, reliability, rich power
saving method and extreme low operating
current, IP101G provides a serial tool for
system designers to complete their projects
easily. They are System Debug Assistant Tool
and EMI Management Tool.
IP101G is fabricated with advanced CMOS
(85nm) technology and design is based on
IC Plus’s 5th Ethernet-PHY architecture, this
feature makes IP101G consumes very low
power. Such as in the full load operation
(100Mbps_FDX), it only takes below 0.15W.
IP101GA / IP101GR&IP101GRI are available in
48LQFP/32QFN, lead-free package.
* EMIMT: Patent under apply.
Application
■
■
■
■
NAS
Network Printers and Servers
IP Set-Top Box
IP/Smart TV
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Game console
IP and Video Phone
PoE
Telecom Fiber device
December 24 2012
IP101G-DS-R01
Copyright © 2011, IC Plus Corp.
www.BDTIC.com/ICplus
IP101G
Preliminary Data Sheet
Table Of Contents
Table Of Contents.................................................................................................................................... 2
List of Figures .......................................................................................................................................... 4
List of Tables............................................................................................................................................ 5
Revision History....................................................................................................................................... 6
Features comparison between IP101G and IP101A/IP101AH ............................................................... 7
Transmit and Receive Data Path Block Diagram .................................................................................... 8
1 Pin diagram ...................................................................................................................................... 9
2 Dice pad information .......................................................................................................................11
3 Pin description................................................................................................................................ 12
IP101GA pin description .................................................................................................... 12
3.1
IP101GR/GRI pin description............................................................................................. 16
3.2
4 Register Descriptions ..................................................................................................................... 19
Register Page mode Control Register ............................................................................... 20
4.1
MII Registers ...................................................................................................................... 20
4.2
MMD Control Register ....................................................................................................... 30
4.3
MMD Data Register ........................................................................................................... 31
4.4
RX Counter Register.......................................................................................................... 34
4.5
LED Mode Control Register ............................................................................................... 35
4.6
WOL+ Control Register...................................................................................................... 35
4.7
UTP PHY Specific Control Register ................................................................................... 38
4.8
Digital IO Pin Control Register ........................................................................................... 39
4.9
5 Function Description....................................................................................................................... 41
Major Functional Block Description ................................................................................... 41
5.1
Transmission Description...................................................................................... 41
5.1.1
MII and Management Control Interface ................................................................ 42
5.1.2
RMII Interface ....................................................................................................... 43
5.1.3
Flexible Clock Source ........................................................................................... 45
5.1.4
Auto-Negotiation and Related Information............................................................ 45
5.1.5
Auto-MDIX function............................................................................................... 46
5.1.6
PHY Address Configuration ............................................................................................... 46
5.2
Power Management Tool ................................................................................................... 47
5.3
Auto Power Saving Mode ..................................................................................... 47
5.3.1
IEEE802.3az EEE (Energy Efficient Ethernet) ..................................................... 48
5.3.2
Force power down ................................................................................................ 48
5.3.3
WOL+ operation mode.......................................................................................... 48
5.3.4
LED Mode Configuration.................................................................................................... 52
5.4
LED Blink Timing................................................................................................................ 52
5.5
Repeater Mode .................................................................................................................. 52
5.6
Interrupt.............................................................................................................................. 52
5.7
Miscellaneous .................................................................................................................... 52
5.8
Serial Management Interface............................................................................................. 53
5.9
5.10 Fiber Mode Setting............................................................................................................. 54
Jumbo Frame ..................................................................................................................... 54
5.11
6 Layout Guideline ............................................................................................................................ 55
General Layout Guideline .................................................................................................. 55
6.1
Twisted Pair recommendation............................................................................................ 55
6.2
7 Electrical Characteristics ................................................................................................................ 56
Absolute Maximum Rating ................................................................................................. 56
7.1
DC Characteristics ............................................................................................................. 56
7.2
Crystal Specifications......................................................................................................... 57
7.3
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2/65
December 24 2012
IP101G-DS-R01
IP101G
Preliminary Data Sheet
7.4
AC Timing........................................................................................................................... 58
Reset, Pin Latched-in, Clock and Power Source.................................................. 58
7.4.1
MII Timing ............................................................................................................. 59
7.4.2
RMII Timing........................................................................................................... 60
7.4.3
SMI Timing ............................................................................................................ 61
7.4.4
Thermal Data ..................................................................................................................... 61
7.5
Order Information ........................................................................................................................... 62
Physical Dimensions ...................................................................................................................... 63
48-PIN LQFP...................................................................................................................... 63
9.1
32-PIN QFN ....................................................................................................................... 64
9.2
8
9
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3/65
December 24 2012
IP101G-DS-R01
IP101G
Preliminary Data Sheet
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Flow chart of IP101G ..................................................................................................................8
IP101GA 48 Pin Diagram ............................................................................................................9
IP101GR/GRI 32 Pin Diagram ..................................................................................................10
IP101G dice pad information..................................................................................................... 11
LPI transition .............................................................................................................................43
IP101G/GA/GR/GRI MII Mode with LPI transition Block Diagram............................................43
IP101G/GA/GR/GRI MII Mode without LPI transition Block Diagram.......................................43
IP101G RMII Mode with internal clock Block Diagram .............................................................44
IP101G RMII Mode with external clock Block Diagram ............................................................44
IP101G RMII Clock Application Circuit....................................................................................45
IP101G link speed and EEE ability programming guide .........................................................46
PHY Address Configuration ....................................................................................................47
Magic Packet Format ..............................................................................................................49
Sleep or wake up automatically programming guide ..............................................................50
MAC control sleep or wake up programming guide ................................................................51
MDC/MDIO Format .................................................................................................................53
IP101G Fiber Mode Setting.....................................................................................................54
Reset, Pin Latched-In, Clock and Power Source Timing Requirements.................................58
MII Transmit Timing Requirements .........................................................................................59
MII Receive Timing Specifications ..........................................................................................59
RMII Transmit Timing Requirements.......................................................................................60
RMII Receive Timing Specifications........................................................................................60
SMI Timing Requirements.......................................................................................................61
48-PIN LQFP Dimension.........................................................................................................63
32-PIN QFN Dimension ..........................................................................................................64
Copyright © 2011, IC Plus Corp.
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December 24 2012
IP101G-DS-R01
IP101G
Preliminary Data Sheet
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Features comparison between IP101G and IP101A/IP101AH.....................................................7
Register Map...............................................................................................................................19
Flexible Clock Source Setting.....................................................................................................45
PHY Address Configuration ........................................................................................................47
WOL+ operation mode................................................................................................................49
LED Mode 1 Function .................................................................................................................52
LED Mode 2 Function .................................................................................................................52
LED Blink Timing ........................................................................................................................52
SMI Format .................................................................................................................................53
DC Characteristics....................................................................................................................56
I/O Electrical Characteristics.....................................................................................................56
Pin Latched-in Configuration Resistor ......................................................................................57
Crystal Specifications................................................................................................................57
Reset, Pin Latched-in, Clock and Power Source Timing Requirements ..................................58
MII Transmit Timing Requirements ...........................................................................................59
MII Receive Timing Specifications ............................................................................................59
RMII Transmit Timing Requirements ........................................................................................60
RMII Receive Timing Specifications .........................................................................................60
SMI Timing Requirements ........................................................................................................61
Thermal Data ............................................................................................................................61
Part Number and Package .......................................................................................................62
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5/65
December 24 2012
IP101G-DS-R01
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