NCP1378
PWM Current-Mode
Controller for Free-Running
Quasi-Resonant Operation
The NCP1378 combines a true current mode modulator and
a demagnetization detector to ensure full borderline/critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi-Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 8.0
ms
timer prevents the free-run frequency to exceed 100 kHz (therefore
below the 150 kHz CISPR-22 EMI starting limit), while the skip
adjustment capability lets the user select the frequency at which the
burst foldback takes place.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast Over
Voltage Protection (OVP). Once an OVP has been detected, the IC
permanently latches off.
The NCP1378 also features an efficient protective circuitry that, in
presence of an overcurrent condition, disables the output pulses and
enters a safe burst mode, trying to restart. Once the default has gone,
the device auto-recovers. Finally an internal 1.0 ms Soft-Start
eliminates the traditional startup stress.
The NCP1378 is tailored for low voltage applications having
UVLO thresholds of 8.4 V (on) and 7.5 V (off).
Features
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MARKING
DIAGRAMS
8
8
1
SOIC-8
D SUFFIX
CASE 751
1
1378
ALYW
G
PDIP-7
P SUFFIX
CASE 626B
8
1
A
L, WL
Y, YY
W, WW
G
or G
1
1378P
AWL
YYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
•
•
•
•
•
•
•
•
•
•
•
•
•
Free-Running Borderline/Critical Mode Quasi-Resonant Operation
Latched Overvoltage Protection
Auto-Recovery Short-Circuit Protection Via UVLO Crossover
Current-Mode with Adjustable Skip Cycle Capability
Internal 1.0 ms Soft-Start
Internal Temperature Shutdown
Internal Leading Edge Blanking
500 mA Peak Current Source/Sink Capability
External Latch Triggering, e.g. Via Overtemperature Signal
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
Internal 8.0
ms
Minimum T
OFF
Pb-Free Packages are Available*
PIN CONNECTIONS
Dmg 1
FB 2
CS 3
GND 4
(Top View)
6 V
CC
5 Drv
8 HV
ORDERING INFORMATION
Device
NCP1378DR2
NCP1378DR2G
NCP1378P
NCP1378PG
Package
SOIC-8
SOIC-8
(Pb-Free)
PDIP-7
PDIP-7
(Pb-Free)
Shipping
†
2500 Tape & Reel
2500 Tape & Reel
50 Units/Rail
50 Units/Rail
Typical Applications
•
Battery-Based Operations
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP1378/D
©
Semiconductor Components Industries, LLC, 2007
1
May, 2007 - Rev. 5
NCP1378
R*
+
12 V @ 1 A
GND
+
Universal
Network
OVP and
Demag
NCP1378
1
2
3
4
8
7
6
5
+
*Please refer to the application information section.
Y1 Type
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION
Pin
1
2
Symbol
Demag
FB
Function
Core reset detection and OVP
Sets the peak current setpoint
Description
The auxiliary FLYBACK signal ensures discontinuous operation and offers a
fixed overvoltage detection level of 5.2 V.
By connecting an optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. By bringing this pin below
the internal skip level, you shut off the device.
This pin senses the primary current and routes it to the internal comparator
via an L.E.B. By inserting a resistor in series with the pin, you control the
level at which the skip operation takes place.
-
The driver's output to an external MOSFET.
This pin is connected to an external bulk capacitor of typically 47
mF.
This unconnected pin ensures adequate creepage distance.
Connected to the high-voltage rail, this pin injects a constant current into the
V
CC
bulk capacitor and ensures a clean lossless startup sequence.
3
CS
Current sense input and skip
cycle level selection
The IC ground
Driving pulses
Supplies the IC
-
High-voltage pin
4
5
6
7
8
GND
Drv
V
CC
NC
HV
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2
NCP1378
4.5
ms
Delay
HV
Demag
4 mA
PON
5.2 V
+
+
+
V
CC
8.4 V
7.5 V
5.6 V (Fault)
Fault
Mngt.
+
-
OVP
+
S
Q
V
CC
Drv
8
ms
Blanking
+
+
50 mV
10 V
Resd
Demag
S*
Q
R* R
Driver src = 20 sink = 10
4.2 V
To Internal
Supply
Soft-Start = 1 ms
/3
1V
200
mA
when DRV
is OFF
Timeout
Reset
340 ns
LEB
Demag
FB
GND
Overload?
5
ms
Timeout
CS
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Power Supply Voltage, V
CC
Pin, Continuous Voltage
Transient Power Supply Voltage, Duration < 10 ms, IV
CC
< 20 mA
Power Supply Voltage
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (V
CC
) and Pin 5 (Drv)
Maximum Current into all pins except V
CC
(6), HV (8) and Demag (1) when 10 V ESD
diodes are activated
Maximum Current in Pin 1
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Air, SOIC Version
Thermal Resistance, Junction-to-Air, PDIP Version
Maximum Junction Temperature
Temperature Shutdown
Hysteresis in Shutdown
Storage Temperature Range
ESD Capability, HBM Model (All pins except V
CC
and HV)
Symbol
V
CC
Static
V
CC
Pulse
V
CC
, Drv
-
-
Idem
R
qJC
R
qJA
R
qJA
TJ
MAX
-
-
-
-
Value
18
25
16
-0.3 to 10
5.0
+3.0/-2.0
57
178
100
150
155
30
-60 to +150
2.0
Unit
V
V
V
V
mA
mA
°C/W
°C/W
°C/W
°C
°C
°C
°C
kV
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3
NCP1378
MAXIMUM RATINGS
Rating
ESD Capability, Machine Model
Maximum Voltage on Pin 8 (HV), Pin 6 (V
CC
) Decoupled to Ground with 10
mF
Symbol
-
V
HV
Value
200
500
Unit
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS
(For typical values T
j
= 25°C, for min/max values T
j
= 0°C to +125°C, Max T
j
= 150°C, V
CC
= 11 V
unless otherwise noted.)
Characteristic
SUPPLY SECTION
V
CC
Increasing Level at which the Current Source Turns-Of f
Minimum Operating Voltage after Turn-On
V
CC
Excursion between VCC
ON
and VCC
OFF
V
CC
Decreasing Level at which the Latchoff Phase Ends
Internal IC Consumption, No Output Load on Pin 5, F
SW
= 60 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
SW
= 60 kHz
Internal IC Consumption, Latchoff Phase, V
CC
= 6.0 V
INTERNAL STARTUP CURRENT SOURCE
(T
j
u
0°C)
High-Voltage Current Source, V
CC
= 7.8 V
High-Voltage Current Source, V
CC
= 0
DRIVE OUTPUT
Output Voltage Rise-Time @ CL = 1.0 nF, 10-90% of Output Signal
Output Voltage Fall-Time @ CL = 1.0 nF, 10-90% of Output Signal
Source Resistance
Sink Resistance
CURRENT COMPARATOR
(Pin 5 not loaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
Propagation Delay from Current Detection to Gate OFF State
Leading Edge Blanking Duration
Internal Current Offset Injected on the CS Pin During OFF Time
OVERVOLTAGE SECTION
(V
CC
= 11 V)
Sampling Delay After ON Time
OVP Internal Reference Level
FEEDBACK SECTION
(V
CC
= 11 V, Pin 5 loaded by 1.0 kW)
Internal Pullup Resistor
Pin 3 to Current Setpoint Division Ratio
Internal Soft-Start
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (Vpin 1 Decreasing)
Hysteresis (Vpin 1 Decreasing)
1
1
V
th
V
H
30
-
50
20
90
-
mV
mV
2
-
-
Rup
Iratio
Tss
-
-
-
20
3.3
1.0
-
-
-
kW
-
ms
1
1
T
sample
V
ref
-
4.6
4.5
5.2
-
6.3
ms
V
3
3
3
3
3
I
IB
I
Limit
T
DEL
T
LEB
Iskip
-
0.9
-
-
-
0.02
1.0
110
340
200
-
1.1
160
-
-
mA
V
ns
ns
mA
5
5
5
5
T
r
T
f
R
OH
R
OL
-
-
10
4.0
40
20
20
10
-
-
36
20
ns
ns
W
W
8
8
IC1
IC2
2.4
-
4.0
4.5
6.0
-
mA
mA
6
6
6
6
6
6
6
VCC
ON
VCC
OFF
VCC
hyst
VCC
latch
ICC1
ICC2
ICC3
7.8
7.0
0.8
-
-
-
-
8.4
7.5
-
5.5
1.0
1.6
220
9.0
8.2
-
-
1.3
(Note 1)
2.0
(Note 1)
-
V
V
-
V
mA
mA
mA
Pin
Symbol
Min
Typ
Max
Unit
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4
NCP1378
DEMAGNETIZATION DETECTION BLOCK
Input Clamp Voltage
High State (Ipin 1 = 3.0 mA)
Low State (Ipin 1 = -2.0 mA)
Demag Propagation Delay
Internal Input Capacitance at Vpin 1 = 1.0 V
Internal Blanking Delay after T
ON
1. Max value at T
j
= 0°C, please see characterization curves.
V
1
1
1
1
1
VC
H
VC
L
T
dem
C
par
T
blank
8.0
-0.9
-
-
-
10
-0.7
240
10
8.0
12
-0.5
-
-
-
ns
pF
ms
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5
