NT5SV8M16HS
128Mb Synchronous DRAM
Feature
Key Timing Parameters
CL=CAS (Read) Latency)
Clock
Speed Grade
Frequency
-75B/-75BI
-6K/-6KI
133 MHz
166 MHz
CL2
10 ns
-
CL3
7.5 ns
6 ns
Time
1.5 ns
1.5 ns
Time
0.8 ns
1.0 ns
Access Time
Setup
Hold
Single pulsed
RAS
Interface
Fully Synchronous to positive clock edge
Four banks controlled by BA0/BA1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8 or full page
Programmable Wrap. Sequential or interleave
Multiple burst read with single write option
Automatic and controlled pre-charge commend
Dual data mask for byte controller
Auto refresh (CBR) and self-refresh
Suspend mode and power down mode
Standard power operation
Random column address every CK (1-N Rule)
Single power supply – 3.3±0.3 V
LVTTL compatible
Packages: 54pin TSOP II
RoHS & Halogen Free Compliant
1
REV 1.7
Dec 2011
CONSUMER DRAM
© NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV8M16HS
128Mb Synchronous DRAM
General Description
The NT5SV8M16HS is four-bank Synchronous DRAMs organized as 2Mbit x 16 I/O x 4 Bank. These synchronous devices
achieve high-speed data transfer rates of up to 166MHz (133MHz) by employing a pipeline chip architecture that
synchronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge
of an externally supplied clock.
RAS, CAS, WE,
and
CS
are pulsed signals which are examined at the positive edge of each externally applied clock (CK).
Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional
RAS/CAS
mul-
tiplexing style. Twelve addresses (A0-A11) and two bank select addresses (BA0, BA1) are strobe with
RAS,
nine column
addresses (A0-A8).
Prior to any access operation, the
CAS
latency, burst length, and burst sequence must be programmed into the device by
address inputs A0-A11, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache operation.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz (or 166MHz) is possible depending on
burst length,
CAS
latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported.
2
REV 1.7
Dec 2011
CONSUMER DRAM
© NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV8M16HS
128Mb Synchronous DRAM
Ordering Information
Standard Grade
Speed
Organization
Part Number
NT5SV8M16HS-75B
NT5SV8M16HS-6K
Package
400mil 54-PIN
TSOPII
Industrial Grade
Speed
Organization
Part Number
NT5SV8M16HS-75BI
NT5SV8M16HS-6KI
Package
400mil 54-PIN
TSOPII
Clock (Mbps)
133
166
Clock (Mbps)
3-3-3
3-3-3
Clock (Mbps)
133
166
CL-T
RCD
-T
RP
3-3-3
3-3-3
8M x 16
8M x 16
3
REV 1.7
Dec 2011
CONSUMER DRAM
© NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV8M16HS
128Mb Synchronous DRAM
Pin Configuration
–
54 Pin TSOPII (x16)
< TOP View>
See the balls through the package
4
REV 1.7
Dec 2011
CONSUMER DRAM
© NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV8M16HS
128Mb Synchronous DRAM
Input / Output Functional Description
Symbol
Type
Function
Clock:
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
Clock Enable:
Activates the CK signal when high and deactivates the CK signal when low. By
CKE
Input
deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh
mode.
Chip Select:
CS
enables the command decoder when low and disables the command decoder
CS
Input
when high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS, WE
Input
Command Inputs:
RAS, CAS
and
WE
(along with
CS)
define the command being entered.
Input Data Mask:
The Data Input/Output mask places the DQ buffers in a high impedance state
when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O
buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output
LDQM, UQDM
Input
buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In
Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be
written if it is low but blocks the write operation if DQM is high.
BA0 – BA1
Input
Bank Address Inputs:
Selects which bank is to be active.
Address Inputs:
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when
sampled at rising edge.
During a Read or Write command cycle, A0-A8 defines the column (CA0-CA8) when sampled at
A0 – A11
Input
rising edge.
During a Precharge command cycle, A10 is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the
bank to be precharged. If A10 is low, autoprecharge is disabled.
DQ0 – DQ15
V
DD
V
SS
V
DDQ
V
SSQ
NC
Input/output
Supply
Supply
Supply
Supply
Data Inputs/Output:
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
Power Supply:
Ground
DQ Power Supply:
DQ Ground
No Connect:
No internal electrical connection is present.
3.3V ± 0.3V
3.3V ± 0.3V
CK
Input
5
REV 1.7
Dec 2011
CONSUMER DRAM
© NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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