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CONTENTS
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CHAPTER 1
INTRODUCTION
................................................................................................................................. 2
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1.1 Features ..................................................................................................................................................................... 2
1.2 Getting Help ............................................................................................................................................................. 3
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CHAPTER 2
ARCHITECTURE & CONFIGURATION
.......................................................................................... 4
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2.1 Block Diagram .......................................................................................................................................................... 5
2.2 Connectivity ............................................................................................................................................................. 7
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CHAPTER 3
PIN DESCRIPTION
........................................................................................................................... 10
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3.1 HSMC Expansion Connector ................................................................................................................................. 10
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CHAPTER 4
COMPONENTS
................................................................................................................................. 18
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4.1 LVDS 28-Bit Channel Link .................................................................................................................................... 18
4.2 3V LVDS Quad CMOS Differential Line Driver ................................................................................................... 18
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4.3 Operation Mode ...................................................................................................................................................... 18
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CHAPTER 5
DEMONSTRATIONS
........................................................................................................................ 21
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5.1 Digital Camera Demonstration for DE4 ................................................................................................................. 21
5.2 Digital Camera Demonstration for DE3 ................................................................................................................. 23
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5.3 Digital Camera Demonstration for DE2-115 .......................................................................................................... 25
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5.4 Digital Camera with PCI Express Interface for DE4 .............................................................................................. 27
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CHAPTER 6
APPENDIX
......................................................................................................................................... 30
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6.1 Revision History ..................................................................................................................................................... 30
6.2 Copyright Statement ............................................................................................................................................... 30
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Chapter 1
0B
Introduction
CLR-HSMC is designed to provide Camera Link connections which are communication interfaces
for vision applications. It uses the High Speed Mezzanine Card (HSMC) to interface with other
mother board hosting HSMC/HSTC carrier such as DE4, DE3 and DE2-115.
1.1 Features
X
Figure 1-1
shows the photo of the CLR-HSMC board. The important features are listed below:
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Support of standard Camera Link modes (base, medium, dual base assembly)
Serial Communication with camera
Simple interface
Automatic detection by hardware / software
Two LVDS 28-bit channel link chip (DS90CR288A)
。28
bit, 20 to 85 MHz shift clock support
。Up
to 2.38 Gbps throughput
。Up
to 297.5 Mbytes/sec bandwidth
Support 2.5V and 3.3 V I/O standard
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Figure 1-1 Picture of the CLR-HSMC Board
1.2 Getting Help
Here are some places to get help if you encounter any problem:
Email to support@terasic.com
Taiwan & China: +886-3-550-8800
Korea : +82-2-512-7661
Japan: +81-428-77-7000
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Chapter 2
1B
Architecture & Configuration
This chapter describes the architecture and configuration of the CLR-HSMC board including block
diagram and components.
Figure 2-1 The CLR-HSMC Board PCB and Component Diagram
A photograph of the CLR-HSMC is shown in
Figure 2-1
and
Figure 2-2
. It depicts the layout of
the board and indicates the location of the connectors and key components.
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