PJESDZ6V8-2G
E.S.D. Dual Protection Diode Array
This Dual Unidirectional ESD Protector Array family have been designed to protect
sensitive equipment against ESD in high speed transmission buses, operating at
5V. This dual array offers an integrated solution to protect up to
2 data lines in a unidirectional mode or, 1 data line in a bi-directional mode, in
application where the board space is a premium, in our SOT523 package
version.
PANJIT SOT523
3
SPECIFICATION FEATURES
IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
Low Leakage Current, Maximum of 0.5µA at rated voltage
Maximum Capacitance of 10pF per device at 0Vdc 1MHz
Peak Power Dissipation of 20W 8/20µs Waveform
Pin to pin compatible with standard SOT523
Lead Free Package 100% Tin Plating, Matte finish
Low profile, Max height of 0.55mm
1
2
3
APPLICATIONS
Mobile Phones
Digital Cameras
Notebooks PC's
1
2
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
ESD Voltage (HBM Per MIL STD883C - Method 3015-6)
Operating Temperature Range
Storage Temperature Range
Symbol
P
PP
I
PPM
V
ESD
TJ
T
stg
Value
20
2
20
-55 to +125
-55 to +150
Units
W
A
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device)
Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Off State Junction Capacitance*
Symbol
V
WRM
V
BR
I
R
V
c
Cj
I
BR
= 1mA
V
R
= 5V
I pp = 2A
0 Vdc Bias f = 1MHz
between pin 1, 2 to 3 (Gnd)
Conditions
Min
Typical
Max
5.0
Units
V
V
µA
V
pF
6.2
7.2
0.5
10
9
10
* Capacitance between pins 1 and 2 is half of the value, in a bi-directional configuration.
12/9/2008
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PJESDZ6V8-2G
TYPICAL CHARACTERISTIC CURVES (Per Device)
Tj = 25°C
Pulse Waveform
110
100
90
80
Percent of Ipp
70
60
50
40
30
20
10
0
0
5
10
15
time, µsec
20
25
30
Rise time 10-90% - 8µs
50% of Ipp @ 20µs
Clamping Voltage vs 8/20µs Ipp
9.5
9
Clamping Voltage, V
8.5
8
7.5
7
6.5
0
0.5
1
1.5
Peak Current, A 8/20µs
2
Off-State Capacitance vs DC Bias
10
Junction Capacitnace, pF
9
8
7
6
5
4
0
1
2
3
Vdc Bias, V
4
5
12/9/2008
Page 2
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PJESDZ6V8-2G
PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT
12/9/2008
Page 3
www.panjit.com
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