PJSMDA05C-7 SERIES
BI-DIRECTIONAL 7-TVS ARRAY
This 7 TVS/Zener Array family have been designed to Protect Sensitive
Equipment against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5V, 12V, 15V and 24V. This TVS array offers an integrated
solution to protect up to 7 data lines where the board space is a premium.
8
7
6
5
SPECIFICATION FEATURES
350W Power Dissipation (8x20µsec Waveform)
Low Leakage Current, Maximum of 5µA at rated voltage
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Packaged in the Industry Standard SOIC-8
100% Tin Matte Finish (RoHS Compliant)
5
1
2
3
4
APPLICATIONS
RS-232C or RS-422 Communication ports
GPIB/IEEE 485 Ports
Portable Instrumentation
Video Signal Ports
8
4
1
SOIC-8
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P
pp
V
ESD
TJ
T
stg
Value
350
>25
-50 to +125
-50 to +150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS
Tj = 25°C
PJSMDA05C-7
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
c
V
c
Cj
Cj
I
BR
= 1mA
V
R
= 5V
I pp = 5A
I pp = 24A
0 Vdc Bias f = 1MHz
Between I/O pins
5 Vdc Bias f = 1MHz
Between I/O pins
Conditions
Min
Typical
Max
5
Units
V
V
6
5
9.5
13
100
60
µA
V
V
pF
pF
4/3/2006
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1
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PJSMDA05C-7 SERIES
ELECTRICAL CHARACTERISTICS
Tj = 25°C
PJSMDA12C-7
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µs)
Clamping Voltage (8x20µs)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
c
V
c
Cj
I
BR
= 1mA
V
R
= 12V
I pp = 5A
I pp = 15A
0 Vdc Bias f = 1MHz
Between I/O pins
Conditions
Min
Typical
Max
12
Units
V
V
13.3
5
17
21
50
µA
V
V
pF
PJSMDA15C-7
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µs)
Clamping Voltage (8x20µs)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
c
V
c
Cj
I
BR
= 1mA
V
R
= 15V
I pp = 5A
I pp = 12A
0 Vdc Bias f = 1MHz
Between I/O pins
Conditions
Min
Typical
Max
15
Units
V
V
16.7
5
22
27
40
µA
V
V
pF
PJSMDA24C-7
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µs)
Clamping Voltage (8x20µs)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
c
V
c
Cj
I
BR
= 1mA
V
R
= 24V
I pp = 5A
I pp = 8A
0 Vdc Bias f = 1MHz
Between I/O pins
Conditions
Min
Typical
Max
24
Units
V
V
26.7
5
35
40
30
µA
V
V
pF
4/3/2006
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PJSMDA05C-7 SERIES
TYPICAL CHARACTERISTICS
TJ = 25°C unless otherwise noted
Surge Pulse Waveform Definition
N
on-R
epetitive Peak Pulse Power vs Pulse Time
Pulse Waveform
Peak Pulse Power - Ppp (W)
110
100
90
80
70
60
50
40
30
20
10
0
0
1000
100
10
1
0.1
0.01
1
10
100
1000
Pulse D
uration, µsec
Percent of Ipp
50% of Ipp @ 20µs
Rise time 10-90% - 8µs
5
10
15
tim e, µsec
20
25
30
Clamping Voltage vs. Peak current
Off-State Capacitance per Device
*
- 1MHz
PJSMDAxxC-7
45
40
35
30
25
20
15
10
5
0
0
5
Clamping voltage, V
24
PJS 24
MS
PJSMDAxxC-7
Per Device
Capacitance, pF
200
180
160
140
120
100
80
60
40
20
0
0
05
PJSMS05
PJS
15
MS
15
PJS
12
MS
12
05
PJS 05
MS
PJSMS1
2
12
15
5
PJSMS1
24
PJSMS24
10
15
20
25
30
1
2
3
4
5
Ipp, A (8/20µsec)
Bias, Vdc
* Note: Capacitance between I/O Lines is half of the
value shown here.
4/3/2006
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PJSMDA05C-7 SERIES
TYPICAL APPLICATION EXAMPLE AND PACKAGE DIMENSIONS
I/O Line1
I/O Line2
I/O Line3
I/O Line4
I/O Line5
I/O Line6
I/O Line7
Ground
5
6
7
4/3/2006
8
1
2
3
4
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PJSMDA05C-7 SERIES
DEVICE MARKING INFORMATION
TVS
PJSMDA05C-7
PJSMDA12C-7
PJSMDA15C-7
PJSMDA24C-7
Marking Code
B05
B12
B15
B24
© Copyright PanJit International, Inc 2006
The information presented in this document is believed to be accurate and reliable. The specifications and information
herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or
systems. Pan Jit does not convey any license under its patent rights or rights of others.
4/4/2006
Page 5
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