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PJSR05_06

Low Capacitance TVS and Diode Array

厂商名称:强茂(PANJIT)

厂商官网:http://www.panjit.com.tw/

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PJSR05
Low Capacitance TVS and Diode Array
This diode array is configured to protect up to two data transmission lines
acting as a line terminator, minimizing overshoot and undershoot conditions
due to bus impedance as well as protect against over-voltage events as
electrostatic discharges. Additionaly the TVS Device offers overvoltage
transient protection between the operating voltage bus and ground plane.
3
4
2
SPECIFICATION FEATURES
Peak Power Dissipation of 350W 8/20µs
Maximum Capacitance of 5.0pF at 0Vdc 1MHz Line-to-Ground
Maximum Leakage Current of 1µA @ VRWM
Industry Standard SMT Package SOT143
IEC61000-4-2, IEC61000-4-4 and IEC61000-4-5 Full Compliance
100% Tin Matte finish (LEAD-FREE PRODUCT)
VREF
4
I/O2
3
1
2
I/O1
1
GND
APPLICATIONS
USB 2.0 and Firewire Port Protection
LAN/WLAN Access Point terminals
Video Signal line protection
I
2
C Bus Protection
SOT143
Marking Code: SL3
SL3
MAXIMUM RATINGS
Tj = 25°C Unless otherwise noted
Rating
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
Operating Junction Temperature Range
Storage Temperature Range
Soldering Temperature, t max = 10s
Symbol
P
PPM
I
PP
T
J
T
stg
T
L
Value
350
17.5
-55 to +125
-55 to +150
260
Units
W
A
°C
°C
°C
3/24/2006
Page 1
www.panjit.com
PJSR05
ELECTRICAL CHARACTERISTICS
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
c
V
c
V
c
Cj
I
BR
= 1mA
V
R
= 5V
I pp = 1A
I pp = 10A
I pp = 17.5A
0 Vdc Bias f = 1MHz
Between I/O pins and GND
0 Vdc Bias f = 1MHz
Between I/O pins
Tj = 25°C unless otherwise noted
Conditions
Min
Typical
Max
5
6.2
1
9.5
12
20
5
3
Units
V
V
µA
V
V
V
pF
pF
TYPICAL CHARACTERISTIC CURVES
Surge Pulse Waveform Definition
Pulse Waveform
110
100
90
80
70
60
50
40
30
20
10
0
0
Non-Repetitive Peak Pulse Power vs Pulse Time
1000
Peak Pulse Power - Ppp (W)
100
10
1
0.1
0.01
1
10
100
1000
Pulse Duration, µsec
Percent of Ipp
50% of Ipp @ 20µs
Rise time 10-90% - 8µs
5
10
15
tim e, µsec
20
25
30
Clamping Voltage vs Ipp 8/20µs Surge
25
20
Ipp, Amps
15
10
5
0
6
7
8
9
10
11
12
13
14
15
Clamping Voltage, V
C, pF
Off-State Capacitance
Line to GND
4
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
Bias Voltage, Vdc
3/24/2006
Page 2
www.panjit.com
PJSR05
PACKAGE DIMENSIONS - SOT143
© Copyright PanJit International, Inc 2006
The information presented in this document is believed to be accurate and reliable. The specifications and information herein are
subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any
license under its patent rights or rights of others.
3/24/2006
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www.panjit.com
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