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PL-2501 Hi-Speed USB Host-to-Host

Bridge/Network Controller

Product Datasheet

Document Revision: 1.3

Document Release: June 11, 2007

Prolific Technology Inc.

7F, No. 48, Sec. 3, Nan Kang Rd.

Nan Kang, Taipei 115, Taiwan, R.O.C.

Tel: 886-2-2654-6363

Fax: 886-2-2654-6161

Email:

sales@prolific.com.tw

URL:

http://www.prolific.com.tw

Revised Date:

June 11, 2007

ds_pl2501_v1.3.doc

Disclaimer

All the information in this document is subject to change without prior notice. Prolific Technology Inc.

does not make any representations or any warranties (implied or otherwise) regarding the accuracy

and completeness of this document and shall in no event be liable for any loss of profit or any other

commercial damage, including but not limited to special, incidental, consequential, or other damages.

Trademarks

The Prolific logo is a registered trademark of Prolific Technology Inc. All brand names and product

names used in this document are trademarks or registered trademarks of their respective holders.

Copyrights

No part of this document may be reproduced or transmitted in any form by any means without the

express written permission of Prolific Technology Inc.

PL-2501 Product Datasheet

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Document Version 1.3

Revised Date:

June 11, 2007

ds_pl2501_v1.3.doc

Revision History

Revision

1.3

1.2

Description

Added Ordering Information section (for Chip Rev C).

Modify Package Outline Diagram.

Add USB-IF and WHQL Logo information.

Add Chip Revision History section (Chip Revision C)

Modify Table 4-1 (Configurations for Different Operation

Modes) to set PL-2501 as default mode.

Add DC Characteristics – Release to Customers

Initial Release – PL2501 Hi-Speed USB 2.0 Host-to-Host

Network Bridge Controller

Date

June 11, 2007

June 6, 2007

1.1

1.0

0.9

February 2003

November 2002

October 2002

PL-2501 Product Datasheet

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Document Version 1.3

Revised Date:

June 11, 2007

ds_pl2501_v1.3.doc

Table of Contents

1.0 INTRODUCTION................................................................................................. 6

2.0 FEATURES ......................................................................................................... 6

3.0 FUNCTIONAL BLOCK ....................................................................................... 7

3.1 Block Diagram ........................................................................................................... 7

3.2 Block Description ...................................................................................................... 8

4.0 SYSTEM DESCRIPTION.................................................................................... 9

4.1 Operation Modes....................................................................................................... 9

5.0 PIN ASSIGNMENT AND DESCRIPTION........................................................... 10

5.1 Pin Assignment and Description of PL-2501 LQFP100........................................... 10

5.2 Pin Assignment and Description of PL-2501 LQFP64..............................................11

6.0 DC CHARACTERISTICS................................................................................... 15

6.1 Absolute Maximum Ratings .................................................................................... 15

6.2 Recommended Operating Conditions ..................................................................... 15

6.3 Leakage Current and Capacitance

(3)

....................................................................... 15

6.4 DC Characteristics of 2.5V Programmable I/O Cells............................................... 16

6.5 DC Characteristics of 3.3V Programmable I/O Cells............................................... 16

7.0 ORDERING INFORMATION............................................................................. 16

8.0 OUTLINE DIAGRAM ......................................................................................... 17

8.1 LQFP100 Package.................................................................................................. 17

8.2 LQFP64 Package.................................................................................................... 18

9.0 CHIP REVISION HISTORY ................................................................................ 19

PL-2501 Product Datasheet

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Document Version 1.3

Revised Date:

June 11, 2007

ds_pl2501_v1.3.doc

List of Figures

Figure 3-1 Block Diagram ....................................................................................................... 7

Figure 3-2 FIFO Structure ....................................................................................................... 7

Figure 5-1 Pin Assignment of PL-2501 LQFP100 ................................................................. 10

Figure 5-2 Pin Assignment of PL-2501 LQFP64 ....................................................................11

Figure 8-1 Outline Diagram of PL-2501 LQFP100................................................................ 17

Figure 8-2 Outline Diagram of PL-2501 LQFP64.................................................................. 18

List of Tables

Table 4-1 Configurations for Different Operation Modes......................................................... 9

Table 5-1 USB2.0 Phy_A related pins................................................................................... 12

Table 5-2 USB2.0 Phy_B related pins................................................................................... 12

Table 5-3 Internal 8032 MCU related pins ............................................................................ 13

Table 5-4 System Pins .......................................................................................................... 13

Table 6-1 Absolute Maximum Ratings................................................................................... 15

Table 6-2 Recommended Operating Conditions ................................................................... 15

Table 6-3 Leakage Current and Capacitance........................................................................ 15

Table 6-4 DC Characteristics of 2.5V Programmable I/O Cells............................................. 16

Table 6-4 DC Characteristics of 3.3V Programmable I/O Cells............................................. 16

Table 7-1 Ordering Information ............................................................................................. 16

Table 9-1 Chip Revision History............................................................................................ 19

PL-2501 Product Datasheet

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Document Version 1.3

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