RTL8201CL
RTL8201CL-LF
RTL8201CL-VD
RTL8201CL-VD-LF
SINGLE-CHIP/SINGLE-PORT
10/100M FAST ETHERNET PHYCEIVER
DATASHEET
Rev. 1.24
04 November 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
RTL8201CL
Datasheet
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
ii
Track ID: JATR-1076-21 Rev. 1.24
RTL8201CL
Datasheet
REVISION HISTORY
Revision
1.0
1.1
1.2
Release Date
2003/06/09
2003/09/26
2004/01/20
Summary
First release.
Minor cosmetic changes.
Modify LED Pin behavior.
Add LED multi-mode definition (7.5 LED and PHY Address
Configuration, page 19).
Add Power dissipation info (Table 31).
Bit <0:8> default setting changed to 0 (Table 9).
Bit <0:13> default setting changed to 0 (Table 9).
Bit <5:7> default setting changed to 0 (Table 14).
Bit <17:5> default setting changed to 1 (Table 17).
Bit <25:0> default setting changed to 0 (Table 20).
Bit <25:1> default setting changed to 0 (Table 20).
Bit <25:11~7> default setting changed to 00001 (Table 20).
Package additions. See section 10, Ordering Information, page 33.
Correction to Table 18, Register 18 RX_ER Counter (REC), page 13.
Correction to Table 39, Transformer Characteristics, page 30.
Added lead (Pb)-free package identification information on page 3 and on
page 33.
Corrected error in 7.8.3 10Base-T TX/RX, page 21 (10Base-T Transmit
Function _ clock at 25MHz => clock at 2.5MHz).
Corrections to Table 32, Input Voltage: Vcc, page 23.
Vcc _ TTL Voh _ Minimum 0.9*Vcc => Minimum 0.65*Vcc
Vcc _ TTL Vol _ Maximum 0.1*Vcc => Maximum 0.3*Vcc
Vcc _ TTL Ioz _ Minimum -10uA => Minimum -110uA
Vcc _ Iin _ Minimum -1.0uA => Minimum -110uA
Vcc _ Iin _ Maximum 1.0uA => Maximum 100uA
Revised Table 1, page 4 (pins 2, 3, 4, 5, 6, and 25).
Corrected Table 17, page 12 (bits 17:6 and 17:5).
Corrected Table 18, page 13 (mode).
Revised Table 32, page 23 (I
IN,
I
PL,
I
PH
).
Revised Table 33, page 24 (t
8
).
Revised Table 34, page 25 (t
6,
t
7,
t
9
).
1.21
1.22
2004/10/12
2005/04/11
1.23
2005/07/29
1.24
2005/11/04
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
iii
Track ID: JATR-1076-21 Rev. 1.24
RTL8201CL
Datasheet
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION................................................................................................................................................1
FEATURES...........................................................................................................................................................................1
BLOCK DIAGRAM.............................................................................................................................................................2
PIN ASSIGNMENTS ...........................................................................................................................................................3
4.1.
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
6.
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.12.
7.
7.1.
7.1.1.
7.1.2.
7.2.
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.8.1.
7.8.2.
7.8.3.
7.9.
7.10.
L
EAD
(P
B
)-F
REE
P
ACKAGE
I
DENTIFICATION
................................................................................................................3
MII I
NTERFACE
............................................................................................................................................................4
SNI (S
ERIAL
N
ETWORK
I
NTERFACE
) 10M
BPS
O
NLY
....................................................................................................5
C
LOCK
I
NTERFACE
.......................................................................................................................................................5
10M
BPS
/100M
BPS
N
ETWORK
I
NTERFACE
....................................................................................................................6
D
EVICE
C
ONFIGURATION
I
NTERFACE
...........................................................................................................................6
LED I
NTERFACE
/PHY A
DDRESS
C
ONFIGURATION
.......................................................................................................6
P
OWER AND
G
ROUND
P
INS
..........................................................................................................................................7
R
ESET AND
O
THER
P
INS
...............................................................................................................................................7
R
EGISTER
0 B
ASIC
M
ODE
C
ONTROL
R
EGISTER
............................................................................................................8
R
EGISTER
1 B
ASIC
M
ODE
S
TATUS
R
EGISTER
...............................................................................................................9
R
EGISTER
2 PHY I
DENTIFIER
R
EGISTER
1....................................................................................................................9
R
EGISTER
3 PHY I
DENTIFIER
R
EGISTER
2....................................................................................................................9
R
EGISTER
4 A
UTO
-N
EGOTIATION
A
DVERTISEMENT
R
EGISTER
(ANAR) ....................................................................10
R
EGISTER
5 A
UTO
-N
EGOTIATION
L
INK
P
ARTNER
A
BILITY
R
EGISTER
(ANLPAR)......................................................10
R
EGISTER
6 A
UTO
-N
EGOTIATION
E
XPANSION
R
EGISTER
(ANER) .............................................................................11
R
EGISTER
16 NW
AY
S
ETUP
R
EGISTER
(NSR).............................................................................................................12
R
EGISTER
17 L
OOPBACK
, B
YPASS
, R
ECEIVER
E
RROR
M
ASK
R
EGISTER
(LBREMR) .................................................12
R
EGISTER
18 RX_ER C
OUNTER
(REC) .....................................................................................................................13
R
EGISTER
19 SNR D
ISPLAY
R
EGISTER
.......................................................................................................................13
R
EGISTER
25 T
EST
R
EGISTER
.....................................................................................................................................13
MII
AND
M
ANAGEMENT
I
NTERFACE
..........................................................................................................................14
Data Transition.....................................................................................................................................................14
Serial Management...............................................................................................................................................15
A
UTO
-N
EGOTIATION AND
P
ARALLEL
D
ETECTION
......................................................................................................16
Setting the Medium Type and Interface Mode to MAC.........................................................................................16
UTP Mode and MII Interface ...............................................................................................................................16
UTP Mode and SNI Interface ...............................................................................................................................17
Fiber Mode and MII Interface..............................................................................................................................17
F
LOW
C
ONTROL
S
UPPORT
..........................................................................................................................................17
H
ARDWARE
C
ONFIGURATION AND
A
UTO
-N
EGOTIATION
............................................................................................18
LED
AND
PHY A
DDRESS
C
ONFIGURATION
................................................................................................................19
S
ERIAL
N
ETWORK
I
NTERFACE
....................................................................................................................................20
P
OWER
D
OWN
, L
INK
D
OWN
, P
OWER
S
AVING
,
AND
I
SOLATION
M
ODES
......................................................................20
M
EDIA
I
NTERFACE
.....................................................................................................................................................20
100Base-TX ..........................................................................................................................................................20
100Base-FX Fiber Mode Operation.....................................................................................................................21
10Base-T TX/RX ...................................................................................................................................................21
R
EPEATER
M
ODE
O
PERATION
.....................................................................................................................................22
R
ESET
,
AND
T
RANSMIT
B
IAS
......................................................................................................................................22
iv
Track ID: JATR-1076-21 Rev. 1.24
PIN DESCRIPTIONS ..........................................................................................................................................................4
REGISTER DESCRIPTIONS ............................................................................................................................................8
FUNCTIONAL DESCRIPTION.......................................................................................................................................14
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
RTL8201CL
Datasheet
7.11.
7.12.
8.
8.1.
8.1.1.
8.1.2.
8.1.3.
8.1.4.
8.2.
8.2.1.
8.2.2.
8.2.3.
8.2.4.
8.2.5.
8.3.
8.4.
9.
10.
9.1.
3.3V P
OWER
S
UPPLY AND
V
OLTAGE
C
ONVERSION
C
IRCUIT
.......................................................................................22
F
AR
E
ND
F
AULT
I
NDICATION
......................................................................................................................................22
DC C
HARACTERISTICS
...............................................................................................................................................23
Absolute Maximum Ratings ..................................................................................................................................23
Operating Conditions ...........................................................................................................................................23
Power Dissipation ................................................................................................................................................23
Input Voltage: Vcc ................................................................................................................................................23
AC C
HARACTERISTICS
...............................................................................................................................................24
MII Transmission Cycle Timing............................................................................................................................24
MII Reception Cycle Timing .................................................................................................................................25
SNI Transmission Cycle Timing............................................................................................................................27
SNI Reception Cycle Timing .................................................................................................................................28
MDC/MDIO Timing..............................................................................................................................................29
C
RYSTAL
C
HARACTERISTICS
......................................................................................................................................30
T
RANSFORMER
C
HARACTERISTICS
............................................................................................................................30
M
ECHANICAL
D
IMENSIONS
N
OTES
............................................................................................................................32
ORDERING INFORMATION......................................................................................................................................33
CHARACTERISTICS .......................................................................................................................................................23
MECHANICAL DIMENSIONS .......................................................................................................................................31
List of Tables
Table 1. MII Interface..................................................................................................................................4
Table 2. SNI (Serial Network Interface) 10Mbps Only ..............................................................................5
Table 3. Clock Interface ..............................................................................................................................5
Table 4. 10Mbps/100Mbps Network Interface............................................................................................6
Table 5. Device Configuration Interface .....................................................................................................6
Table 6. LED Interface/PHY Address Configuration..................................................................................7
Table 7. Power and Ground Pins .................................................................................................................7
Table 8. Reset and Other Pins......................................................................................................................7
Table 9. Register 0 Basic Mode Control Register .......................................................................................8
Table 10. Register 1 Basic Mode Status Register..........................................................................................9
Table 11. Register 2 PHY Identifier Register 1.............................................................................................9
Table 12. Register 3 PHY Identifier Register 2.............................................................................................9
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)..................................................10
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) ....................................10
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) .........................................................11
Table 16. Register 16 NWay Setup Register (NSR)....................................................................................12
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) ..............................12
Table 18. Register 18 RX_ER Counter (REC)............................................................................................13
Table 19. Register 19 SNR Display Register ..............................................................................................13
Table 20. Register 25 Test Register.............................................................................................................13
Table 21. Serial Management ......................................................................................................................15
Table 22. Setting the Medium Type and Interface Mode to MAC..............................................................16
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
v
Track ID: JATR-1076-21 Rev. 1.24
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