CCD image sensors
S14650/S14660 series
Photosensitive area structure suitable for spectrometers,
high-speed type and low-noise type available
The S14650/S14660 series are back-thinned CCD image sensors designed for spectrometers. Low-noise type (S14650 series)
and high-speed type (S14660 series) are available.
The S14650/S14660 series offer nearly flat spectral response characteris-
tics with high quantum efficiency from the UV to near infrared region.
Features
Low etaloning
High sensitivity over a wide spectral range and
nearly flat spectral response characteristics
High conversion efficiency: 6.5 µV/e- (S14650 series)
8 µV/e- (S14660 series)
High full well capacity and wide dynamic range
(horizontal shift register with anti-blooming function)
Pixel size: 14 × 14 µm
Applications
Spectrometers and the like
Selection guide
Type no.
S14650-1024
S14650-2048
S14660-1024
S14660-2048
Total number of pixels
1044
2068
1044
2068
×
×
×
×
198
198
198
198
Number of effective pixels
1024
2048
1024
2048
×
×
×
×
192
192
192
192
Image size
[mm (H) ×
mm (V)]
14.336
28.672
14.336
28.672
×
×
×
×
2.688
2.688
2.688
2.688
Readout speed
max.
(MHz)
0.5
10
Structure
Parameter
S14650 series
S14660 series
Pixel size (H × V)
14 × 14 µm
Vertical clock
2-phase
Horizontal clock
4-phase
Output circuit
One-stage MOSFET source follower
Two-stage MOSFET source follower
Package
24-pin ceramic DIP (refer to dimensional outlines)
1
Window material*
Quartz glass*
2
Cooling
Non-cooled
*1:
Temporary window type (examples: S14650-2048N, S14660-2048N) is also available upon request.
*2:
Resin sealing
www.hamamatsu.com
1
CCD image sensors
S14650/S14660 series
Absolute maximum ratings (Ta=25 °C)
Parameter
Operating temperature*
3
Storage temperature
Output transistor S14650 series
drain voltage
S14660 series
Reset drain voltage
Output amplifier return voltage
Overflow drain voltage
Vertical input source voltage
Horizontal input source voltage
Overflow gate voltage
Vertical input gate voltage
Horizontal input gate voltage
Summing gate voltage
Output gate voltage
Reset gate voltage
Transfer gate voltage
Vertical shift register clock voltage
Horizontal shift register clock voltage
Symbol
Topr
Tstg
V
OD
V
RD
Vret
V
OFD
V
ISV
V
ISH
V
OFG
V
IGV
V
IGH
V
SG
V
OG
V
RG
V
TG
V
P1V
, V
P2V
V
P1H
, V
P2H
V
P3H
, V
P4H
Tsol
Min.
-50
-50
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-10
-10
-10
-10
-10
-10
-10
-10
-10
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
+50
+70
+30
+25
+18
+18
+18
+18
+18
+15
+15
+15
+15
+15
+15
+15
+15
+15
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Soldering conditions*
4
260 °C, within 5 s, at least 2 mm away from lead roots
-
*3:
Package temperature
*4:
Use a soldering iron.
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
Operating conditions (MPP mode, Ta=25 °C)
Parameter
Output transistor drain voltage
Reset drain voltage
Overflow drain voltage
Overflow gate voltage
Output gate voltage
Substrate voltage
Output amplifier return voltage*
5
Input source
Test point
Vertical input gate
Horizontal input gate
High
Vertical shift register clock voltage
Low
Horizontal shift register clock voltage
Summing gate voltage
Reset gate voltage
Transfer gate voltage
High
Low
High
Low
High
Low
High
Low
Symbol
Min.
23
11
11
0
4
-
S14650 series
Typ.
24
12
12
12
5
0
Max.
25
13
13
13
6
-
-
-
-
8
-7
8
-4
8
-4
8
-4
8
-7
110
voltage, but
Min.
12
14
11
0
4
-
-
-
-9
-9
4
-9
4
-6
S14660 series
Typ.
15
15
12
13
5
0
1
V
RD
-8
-8
6
-8
6
-5
Max.
18
16
13
14
6
-
2
-
-
-
8
-7
8
-4
Unit
V
V
V
V
V
V
V
V
V
V
External load resistance
*5:
Output amplifier return voltage is
V
OD
V
RD
V
OFD
V
OFG
V
OG
V
SS
Vret
V
ISV
, V
ISH
-
V
RD
V
IGV
-9
-8
V
IGH
-9
-8
V
P1VH
, V
P2VH
4
6
V
P1VL
, V
P2VL
-9
-8
V
P1HH
, V
P2HH
4
6
V
P3HH
, V
P4HH
V
P1HL
, V
P2HL
-6
-5
V
P3HL
, V
P4HL
V
SGH
4
6
V
SGL
-6
-5
V
RGH
4
6
V
RGL
-6
-5
V
TGH
4
6
V
TGL
-9
-8
R
L
90
100
a positive voltage with respect to substrate
4
6
8
V
-6
-5
-4
4
6
8
V
-6
-5
-4
4
6
8
V
-9
-8
-7
2.0
2.2
2.4
kΩ
the current flows out from the sensor.
2
CCD image sensors
S14650/S14660 series
Electrical characteristics [Ta=25 °C, operating conditions: Typ. value (P.2)]
Parameter
Output signal frequency*
6
-1024
Vertical shift register
capacitance
-2048
Horizontal shift register -1024
capacitance
-2048
Summing gate capacitance
Reset gate capacitance
-1024
Transfer gate capacitance
-2048
7
Charge transfer efficiency*
DC output level*
6
Output impedance*
6
Power consumption*
6
*
8
Symbol
fc
C
P1V
, C
P2V
C
P1H
, C
P2H
C
P3H
, C
P4H
C
SG
C
RG
C
TG
C
TE
Vout
Zo
P
S14650 series
Min.
Typ.
-
0.25
-
1800
-
3600
-
80
-
160
-
10
-
10
-
30
-
60
0.99995
0.99999
17
18
-
10
-
4
Max.
0.5
-
-
-
-
-
-
-
-
-
19
-
-
S14660 series
Min.
Typ.
-
5
-
1800
-
3600
-
80
-
160
-
10
-
10
-
30
-
60
0.99995
0.99999
7
8
-
0.3
-
75
Max.
10
-
-
-
-
-
-
-
-
-
9
-
-
Unit
MHz
pF
pF
pF
pF
pF
-
V
kΩ
mW
*6:
The values depend on the load resistance (S14650 series: V
OD
=24 V, R
L
=100 kΩ, S14660 series: V
OD
=15 V, R
L
=2.2 kΩ)
*7:
Charge transfer efficiency per pixel, measured at half of the full well capacity
*8:
Power consumption of the on-chip amp plus load resistance
Electrical and optical characteristics [Ta=25 °C, operating conditions: Typ. value (P.2), unless otherwise noted]
Parameter
Saturation output voltage
Vertical
Full well capacity
Horizontal
9
Conversion
efficiency*
Dark current*
10
Readout noise*
11
Dynamic range*
12
Line binning
Spectral response range
Photoresponse nonuniformity*
13
Symbol
Vsat
Fw
CE
DS
Nr
DR
λ
PRNU
S14650 series
Min.
Typ.
-
Fw × Sv
50
60
250
300
5.5
6.5
-
50
-
6
41700
50000
-
200 to 1100
-
±3
Max.
-
-
-
7.5
500
15
-
-
±10
S14660 series
Min.
Typ.
-
Fw × Sv
50
60
150
200
7
8
-
50
-
30
5000
6660
-
200 to 1100
-
±3
Max.
-
-
-
9
500
45
-
-
±10
Unit
V
ke-
µV/e
-
e-/pixel/s
e- rms
-
nm
%
*9:
The values depend on the load resistance (S14650 series: V
OD
=24 V, R
L
=100 kΩ, S14660 series: V
OD
=15 V, R
L
=2.2 kΩ)
*10:
Dark current nearly doubles for every 5 to 7 °C increase in temperature.
*11:
S14650 series (temperature: -40 °C): fc=20 kHz, S14660 series (temperature: 25 °C): fc= 5 MHz
*12:
Dynamic range = saturation charge/readout noise
*13:
Measured at half the saturation output using an LED light (peak emission wavelength: 660 nm)
Fixed pattern noise (peak to peak)
Photoresponse nonuniformity =
× 100 [%]
Signal
3
CCD image sensors
S14650/S14660 series
Spectral response (without window)*
14
100
(Typ. Ta=25 °C)
0.5
(Typ. Ta=25 °C)
80
0.4
Quantum efficiency (%)
60
Photosensitivity (A/W)
0.3
40
0.2
20
Spectral transmittance of window material (quartz glass)
(S10420-1006/-1106, S11071/S10420-01 series)
0
200
0.1
Dark current vs. temperature
400
600
800
1000
1200
0
200
400
600
800
1000
1200
Wavelength (nm)
KMPDB0316EA
Wavelength (nm)
KMPDB0440EA
*14:
Spectral response will degrade depending on the transmittance
characteristics of the quartz glass.
Spectral transmittance characteristics of window material
100
(Typ. Ta=25 °C)
Dark current vs. temperature
1000
KMPDB0316EA
100
(Typ.)
KMPDB0440
80
Dark current (e-/pixel/s)
Transmittance (%)
60
10
40
1
20
0.1
0
200 300
400 500
600 700 800 900 1000 1100
0.01
-50 -40 -30 -20 -10
0
10
20
30
40
50
Wavelength (nm)
KMPDB0303EB
Temperature (°C)
KMPDB0304EB
KMPDB0303EB
KMPDB0304
4
CCD image sensors
Device structure
S14650/S14660 series
Device structure (schematic of CCD chip as viewed from top of dimensional outline)
S14650 series
Effective
pixels
Thinning
Effective pixels
23
22
21
20
18
17
16
15
Horizontal shift register
24
5
4
3
2
1 2 3 4 5
14
H
13
192 signal output
4-bevel
H=1024, 2048
192
Thinning
1
2
3
4
5
6
7
8
9
10
12
4 blank pixels
Horizontal shift register
6-bevel
2
n
signal output
4 blank pixels
6-bevel
Device structure
Note: When viewed from the light input side, the horizontal shift register is covered by the
thick area of the silicon (insensitive area), but long-wavelength light may pass through
the insensitive silicon area. This light may be received by the horizontal shift register.
Take measures such as shielding the light.
KMPDC0698EA
S14660 series
Effective
pixels
Thinning
KMPDC0698EA
Effective pixels
23
22
21
20
18
17
16
15
Horizontal shift register
24
5
4
3
2
1 2 3 4 5
14
H
13
192 signal output
4-bevel
H=1024, 2048
192
Thinning
2
1
5
3
4
6
7
8
9
10
12
4 blank pixels
Horizontal shift register
6-bevel
2
n
signal output
4 blank pixels
6-bevel
Note: When viewed from the light input side, the horizontal shift register is covered by the
thick area of the silicon (insensitive area), but long-wavelength light may pass through
the insensitive silicon area. This light may be received by the horizontal shift register.
Take measures such as shielding the light.
KMPDC0697EA
2-bevel
2-bevel
5
KMPDC0697EA
微控制器 MCU
