SC92031
10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS
CONTROLLER AND PHYSICAL LAYER
DESCRIPTION
The SC92031 is a highly-integrated and cost-effective single-chip
Fast Ethernet NIC controller. It fully complies with PCI 2.2 and IEEE
802.3u 100Base-T specifications. It supports both half-duplex and full -
duplex operation, as well as for full-duplex flow control. It also supports
Advanced Configuration Power management Interface (ACPI), PCI
power management and remote wake-up events including AMD Magic
Packet, Link Change, and Microsoft® wake-up frame.
The SC92031 provides glue less 32-bit bus master interface for PCI,
boot ROM interface, as well as physical media interface for 100BASE-
TX of IEEE 802.3u and 10BASE-T of 802.3. It also supports shared
Boot ROM pins & clock run pin.
The SC92031 supports Analog Auto-Power-down, that is, the analog
part of the SC92031 can be shut down temporarily according to user
requirement or when the SC92031 is in a power down state with the
wakeup function disabled.
PCI Vital Product Data (VPD) is also supported to provide the
information that uniquely identifies hardware. The information may
consist of part number, serial number, and other detailed information.
To provide cost down, the SC92031 is capable of using a 25MHz
crystal or OSC as its internal clock source.
The SC92031 includes a PCI and Expansion Memory Share Interface
for a boot ROM and can be used in diskless workstations, providing
maximum network security and ease of management.
The SC92031 provides a flexible multi-function mode to incorporate
other PCI master devices. When in multi-function mode, the SC92031
acts as an arbiter to distinguish LAN signals from those of other
devices.
LQFP-100-14x14-0.5
QFP-100-14x20-0.65
ORDERING INFORMATION
Device
SC92031
Package
QFP-100-14 X 20-0.65
SC92031L LQFP-100-14 X 14-0.5
APPLICATIONS
* 10/100Mbps PCI fast Ethernet
adaptor
FEATURES
* Integrated Fast Ethernet MAC, Physical layer and transceiver in one chip
* 10 Mbps and 100 Mbps data rates
* Both half duplex and full duplex available
* IEEE 802.3 compliant Auto-Negotiation
* Supports PCI multi-function capabilities
* PCI local bus
Ø
Compliant to PCI Revision 2.2
Ø
Supports PCI clock 15 MHz-40 MHz
Ø
Supports PCI target fast back-to-back transaction
Ø
Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of
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SC92031
SC92031's operational registers
Ø
Supports PCI VPD (Vital Product Data)
Ø
Supports ACPI 1.0 and PCI power management Ver.1.1 compliant
Ø
Supports PCI multi-function to incorporate with other PCI master device
* Supports 25MHz crystal or 25MHz OSC as the internal clock source.
* Compliant to PC99 and PC2001 standards
* Supports Wake-On-LAN function and remote wake-up (Magic Packet*, Link Change and Microsoft® wake-up
frame)
* Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse)
* Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI
configuration space
* Includes a programmable, PCI burst size and early Tx/Rx threshold
* Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-
interrupt
* Contains two large (2Kbyte) independent receive and transmit FIFOs
* Advanced power saving mode when LAN function or wakeup function is not used
* Uses serial EEPROM to store resource configuration, ID parameter, and VPD data
* Extensive LED status support
* Supports loop back capability
* Supports Full Duplex Flow Control
* Low-power 0.25u CMOS technology
* 3.3V power supply with 5V tolerant I/Os
* 100-pin QFP/LQFP package
* Third-party brands and names are the property of their respective owners.
BLOCK DIAGRAM
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SC92031
ABSOLUTE MAXIMUM RATINGS
(unless otherwise stated, T
amb
=25°C, V
SS
=0V)
Characteristics
Supply Voltage
Input/Output Voltage
Operating Temperature
Storage Temperature
Symbol
V
DD
V
I
, V
O
T
opr
T
stg
Value
0 ~ 4.0
-0.5 ~ V
DD
+0.5
0 ~ 70
-40 ~ 125
Unit
V
V
DC ELECTRICAL CHARACTERISTICS
Characteristics
Minimum High Level Output Voltage
Maximum Low Level Output Voltage
Minimum High Level Input Voltage
Minimum Low Level Input Voltage
Input Current
Tri-state Output Leakage Current
Average operating Supply Current
Symbol
V
OH
V
OL
V
IH
V
IL
I
IN
I
OZ
I
CC
V
IN
=V
DD
or GND
V
OUT
=V
DD
or GND
I
OUT
=0mA
Test Condition
I
OH
=-8mA
I
OL
=8mA
0.5V
DD
-0.5
-1.0
-1.0
Min.
0.9V
DD
Typ.
Max.
V
DD
0.1V
DD
V
DD
+0.5
0.3V
DD
1.0
10
330
Unit
V
V
V
V
µA
µA
mA
Supply voltage V
DD
=3.0V min. to 3.6V max.
PIN CONFIGURATION
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SC92031
PIN CONFIGURATION
75
ACT 76
G_RST 77
REQB2 78
GNTB2 79
SE 80
INTAB 81
RSI_RST 82
PCI_CLK 83
V
DD
84
GNTB 85
REQB 86
PMEB 87
AD31 88
AD30 89
GND 90
AD29 91
AD28 92
AD27 93
AD26 94
AD25 95
AD24 96
V
DD
97
C/BE3B 98
IDSEL 99
AD23
100
1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 CLKR
49 AUX
48 EECS
47 EECK
46 EEDI
45 EEDO
44 AD0
43 AD1
42 V
DD
41 AD2
40 AD3
39 GND
SC92031L
38 GND
37 AD4
36 AD5
35 AD6
34 ROM_OE
33 V
DD
32 AD7
31 C/BE0B
30 GND
29 AD8
28 AD9
27 AD10
26 AD11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN DESCRIPTION
Pin No.
PCI Interface
82
PCI_RST
When RSTB is asserted low, the SC92031 performs internal system
hardware reset. RSTB must be held for a minimum of 120 ns.
This PCI Bus clock provides timing for all transactions and bus phases, and
83
88, 89, 91-96,
100, 1, 3-5, 7-9,
22-29, 32, 35-
37, 40, 41, 43,
44
(To be continued)
Symbol
Description
PCI_CLK
is input to PCI devices. The rising edge defines the start of each phase. The
clock frequency ranges from 0 to 33MHz.
PCI address and data multiplexed pins.
AD31-0
Pins AD31-24 are shared with Boot ROM data pins, while AD16-0 are
shared with Boot ROM address pins.
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SC92031
(Continued)
Pin No.
98, 10, 20, 31
14
11
85
86
99
Symbol
C/BE3-0B
DEVSELB
FRAMEB
GNTB
REQB
IDSEL
Description
PCI bus command and byte enables.
Device Select, target is driving to indicate the address is decoded.
Begin and duration of bus access, driven by master device.
PCI bus granted. This signal indicates that the PCI bus request of SC92031
has been accepted.
PCI bus request, the SC92031 will assert this signal low to request the
ownership of the bus from the central arbiter.
Initialization Device Select. This pin allows the SC92031 to identify when
configuration read/write transactions are intended for it.
PCI interrupt request. It is asserted low when an interrupt condition occurs,
as defined by the Interrupt Status, Interrupt Mask and Interrupt Enable
registers.
Master device is ready to data transaction.
Slave device is ready to data transaction.
Parity, this signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.
Data parity error is detected, driven by the agent receiving data.
Address parity error.
The current target is requesting the master to stop the current transaction.
Power Management Event, Open drain, active low. Used by the SC92031 to
81
12
13
19
16
18
15
INTAB
IRDYB
TRDYB
PAR
PERRB
SERRB
STOPB
Power Management/Isolation Interface
87
PMEB
request a change in its current power management state and/or to indicate
that a power management event has occurred.
LAN WAKE-UP signal, This signal is used to inform the motherboard to
execute the wake-up process. The motherboard must support Wake-On-
71
LWAKE
LAN (WOL). There are 4 choices of output, including active high, active low,
positive pulse, and negative pulse, that may be asserted from the LWAKE
pin.
EEPROM Interface
This pin is used to notify the SC92031 of the existence of Aux. power during
initial power-on or a PCI reset. This pin should be pulled high to the Aux.
49
AUX
power via a resistor to detect the Aux. power. Doing so, will enable wakeup
support from ACPI D3 cold or APM power-down. If this pin is not pulled
high, the SC92031 assumes that no Aux. power exists.
EEPROM Interface
47
46
45
48
EECK
EEDI
EEDO
EECS
EEPROM chip serial clock
EEPROM chip serial data in
EEPROM chip serial data out
EEPROM chip select
(To be continued)
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