Si5345/44/42 Rev D Data Sheet
10-Channel, Any-Frequency, Any-Output Jitter Attenuator/
Clock Multiplier
These jitter attenuating clock multipliers combine fourth-generation DSPLL
™
and
MultiSynth
™
technologies to enable any-frequency clock generation and jitter attenu-
ation for applications requiring the highest level of jitter performance. These devices
are programmable via a serial interface with in-circuit programmable non-volatile
memory (NVM) so they always power up with a known frequency configuration. They
support free-run, synchronous, and holdover modes of operation, and offer both au-
tomatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Furthermore,
the jitter attenuation bandwidth is digitally programmable, providing jitter perform-
ance optimization at the application level. Programming the Si5345/44/42 is easy
with Silicon Labs’
ClockBuilder Pro
™
software. Factory preprogrammed devices are
also available.
Applications:
• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards
• Broadcast video
• Test and measurement
• ITU-T G.8262 (SyncE) compliant
25-54 MHz XTAL
XA
OSC
IN0
4 Input
Clocks
IN1
IN2
÷FRAC
÷FRAC
÷FRAC
÷FRAC
DSPLL
XB
Si5342
MultiSynth
MultiSynth
MultiSynth
MultiSynth
MultiSynth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Status Flags
I2C / SPI
Status Monitor
Control
NVM
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Si5345
OUT8
OUT9
KEY FEATURES
• Generates any combination of output
frequencies from any input frequency
• Ultra-low jitter of 90 fs rms
• External Crystal: 25 to 54 MHz
• Input frequency range
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Meets G.8262 EEC Option 1, 2 (SyncE)
• Highly configurable outputs compatible with
LVDS, LVPECL, LVCMOS, CML, and HCSL
with programmable signal amplitude
• Si5345: 4 input, 10 output, 64-QFN 9×9 mm
• Si5344: 4 input, 4 output, 44-QFN 7×7 mm
• Si5342: 4 input, 2 output, 44-QFN 7×7 mm
Si5344
Up to 10
Output Clocks
IN3/FB_IN
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Rev. 1.2
Si5345/44/42 Rev D Data Sheet
Features List
1. Features List
The Si5345/44/42 Rev D features are listed below:
• Generates any combination of output frequencies from any in-
put frequency
• Ultra-low jitter of 90 fs rms
• Input frequency range
• Differential: 8 kHz–750 MHz
• LVCMOS: 8 kHz–250 MHz
• Output frequency range
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz
• Meets G.8262 EEC Option 1, 2 (SyncE)
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or manual
• Locks to gapped clock inputs
• Free-run and holdover modes
•
•
•
•
•
Optional zero delay mode
Fastlock feature for low nominal bandwidths
Glitchless on the fly output frequency changes
DCO mode: as low as 0.001 ppb step size
Core voltage
• V
DD
: 1.8 V ±5%
• V
DDA
: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I
2
C or SPI
•
•
•
•
•
•
•
In-circuit programmable with non-volatile OTP memory
ClockBuilder Pro
software simplifies device configuration
Si5345: 4 input, 10 output, 64-QFN 9×9 mm
Si5344: 4 input, 4 output, 44-QFN 7×7 mm
Si5342: 4 input, 2 output, 44-QFN 7×7 mm
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
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Rev. 1.2 | 2
Si5345/44/42 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Ordering Part Number
(OPN)
Si5345
Si5345A-D-GM
1, 2
Si5345B-D-GM
1, 2
Si5345C-D-GM
1, 2
Si5345D-D-GM
1, 2
Si5344
Si5344A-D-GM
1, 2
Si5344B-D-GM
1, 2
Si5344C-D-GM
1, 2
Si5344D-D-GM
1, 2
Si5342
Si5342A-D-GM
1, 2
Si5342B-D-GM
1, 2
Si5342C-D-GM
1, 2
Si5342D-D-GM
1, 2
Si5345/44/42-D-EVB
Si5345-D-EVB
Si5344-D-EVB
Si5342-D-EVB
Notes:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the
ClockBuilder
Pro
software. Custom part number format is “Si5345A-Dxxxxx-GM” where “xxxxx” is a unique numerical sequence representing
the preprogrammed configuration.
—
—
—
Evaluation
Board
—
4/2
0.001 to 1028 MHz
0.001 to 350 MHz
0.001 to 1028 MHz
0.001 to 350 MHz
Integer and
Fractional
Integer Only
44-QFN
7×7 mm
–40 to 85 °C
4/4
0.001 to 1028 MHz
0.001 to 350 MHz
0.001 to 1028 MHz
0.001 to 350 MHz
Integer and
Fractional
Integer Only
44-QFN
7×7 mm
–40 to 85 °C
4/10
0.001 to 1028 MHz
0.001 to 350 MHz
0.001 to 1028 MHz
0.001 to 350 MHz
Integer and
Fractional
Integer Only
64-QFN
9×9 mm
–40 to 85 °C
Number of Input/
Output Clocks
Output Clock Frequency Supported Frequency
Range (MHz)
Synthesis Modes
Package
Temperature
Range
silabs.com
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Rev. 1.2 | 3
Si5345/44/42 Rev D Data Sheet
Ordering Guide
Figure 2.1. Ordering Part Number Fields
silabs.com
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Rev. 1.2 | 4
Table of Contents
1. Features List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Ordering Guide
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Frequency Configuration
3.2 DSPLL Loop Bandwidth .
3.3 Fastlock Feature .
.
.
3.4 Modes of Operation . .
3.4.1 Initialization and Reset
3.4.2 Freerun Mode . . .
3.4.3 Lock Acquisition Mode
3.4.4 Locked Mode . . .
3.4.5 Holdover Mode . .
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. 7
. 7
. 7
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7
8
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8
9
3.5 External Reference (XA/XB)
. 9
.10
.10
.10
.11
.11
.11
.11
.12
.13
.13
.14
.14
.14
.15
.16
.16
.17
.17
.18
.18
.18
.19
.19
.19
.19
.19
.19
.20
.20
3.6 Digitally Controlled Oscillator (DCO) Mode
3.7 Inputs (IN0, IN1, IN2, IN3) . . . . . . . .
3.7.1 Manual Input Switching (IN0, IN1, IN2, IN3) .
3.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3)
3.7.3 Hitless Input Switching . . . . . . . .
3.7.4 Ramped Input Switching . . . . . . .
3.7.5 Glitchless Input Switching . . . . . . .
3.7.6 Input Configuration and Terminations . . .
3.7.7 Synchronizing to Gapped Input Clocks . .
3.8 Fault Monitoring . . .
3.8.1 Input LOS Detection.
3.8.2 XA/XB LOS Detection
3.8.3 OOF Detection . .
3.8.4 LOL Detection . . .
3.8.5 Interrupt Pin (INTRb)
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3.9 Outputs . . . . . . . . . . . . . . . . . . . .
3.9.1 Output Crosspoint . . . . . . . . . . . . . . .
3.9.2 Output Signal Format . . . . . . . . . . . . . .
3.9.3 Differential Output Terminations . . . . . . . . . . .
3.9.4 LVCMOS Output Terminations . . . . . . . . . . .
3.9.5 Programmable Common Mode Voltage For Differential Outputs
3.9.6 LVCMOS Output Impedance Selection . . . . . . . .
3.9.7 LVCMOS Output Signal Swing . . . . . . . . . . .
3.9.8 LVCMOS Output Polarity . . . . . . . . . . . . .
3.9.9 Output Enable/Disable . . . . . . . . . . . . . .
3.9.10 Output Driver State When Disabled . . . . . . . . .
3.9.11 Synchronous Output Disable Feature . . . . . . . .
3.9.12 Zero Delay Mode . . . . . . . . . . . . . . .
3.9.13 Output Divider (R) Synchronization . . . . . . . . .
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Rev. 1.2 | 5
嵌入式系统
