Si5347/46 Rev D Data Sheet
Dual/Quad DSPLL
™
Any-Frequency, Any-Output Jitter Attenua-
tors
The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates
four any-frequency DSPLLs for applications that require maximum integration and inde-
pendent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each
DSPLL has access to any of the four inputs and can provide low jitter clocks on any of
the device outputs. Based on 4
th
generation DSPLL technology, these devices provide
any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL
supports independent free-run, holdover modes of operation, as well as automatic and
hitless input clock switching. The Si5347/46 is programmable via a serial interface with
in-circuit programmable non-volatile memory so that it always powers up in a known
configuration. Programming the Si5347/46 is easy with Silicon Labs'
ClockBuilder
Pro™
software. Factory preprogrammed devices are also available.
KEY FEATURES
• Four or two independent DSPLLs, any
output frequency from any input frequency
• Ultra-low jitter of 95 fs rms
• Input frequency range:
• External Crystal: 25–54 MHz
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 720 MHz
• LVCMOS: 100 Hz to 250 MHz
• Status Monitoring
• Hitless switching
• Si5347: 4 input, 8 output, 64-QFN 9×9 mm
• Si5346: 4 input, 4 output, 44-QFN 7×7 mm
Applications
• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video
25-54 MHz XTAL
XA
OSC
IN0
4 Input
Clocks
IN1
IN2
IN3
÷FRAC
÷FRAC
÷FRAC
÷FRAC
DSPLL A
DSPLL B
DSPLL C
DSPLL D
XB
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Status Flags
I2C / SPI
Status Monitor
Control
NVM
OUT0
Si5346A/B
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Si5347A/B
Si5347C/D
silabs.com
| Building a more connected world.
Rev. 1.1
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Frequency Configuration
3.2 DSPLL Loop Bandwidth .
3.2.1 Fastlock Feature . .
3.3 Modes of Operation . .
3.3.1 Initialization and Reset
3.3.2 Free-run Mode . .
3.3.3 Lock Acquisition Mode
3.3.4 Locked Mode . . .
3.3.5 Holdover Mode . .
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. 6
. 6
. 6
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6
6
7
7
7
8
3.4 Digitally-Controlled Oscillator (DCO) Mode
3.5 External Reference (XA/XB)
3.6 Inputs (IN0, IN1, IN2, IN3) . . . . . .
3.6.1 Input Selection . . . . . . . .
3.6.2 Manual Input Selection . . . . . .
3.6.3 Automatic Input Selection . . . . .
3.6.4 Input Configuration and Terminations .
3.6.5 Hitless Input Switching . . . . . .
3.6.6 Ramped Input Switching . . . . .
3.6.7 Glitchless Input Switching . . . . .
3.6.8 Synchronizing to Gapped Input Clocks
3.7 Fault Monitoring . . .
3.7.1 Input LOS Detection.
3.7.2 XA/XB LOS Detection
3.7.3 OOF Detection . .
3.7.4 LOL Detection . . .
3.7.5 Interrupt Pin (INTRb)
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. 8
. 9
.10
.10
.10
.10
.11
.12
.12
.12
.12
.13
.13
.13
.14
.15
.17
.17
.18
.19
.19
.19
.19
.20
.20
.20
.21
.21
.21
.21
.21
3.8 Outputs . . . . . . . . . . . . . . . . . . . .
3.8.1 Output Crosspoint . . . . . . . . . . . . . . .
3.8.2 Differential Output Terminations . . . . . . . . . . .
3.8.3 LVCMOS Output Terminations . . . . . . . . . . .
3.8.4 Output Signal Format . . . . . . . . . . . . . .
3.8.5 Programmable Common Mode Voltage For Differential Outputs
3.8.6 LVCMOS Output Impedance Selection . . . . . . . .
3.8.7 LVCMOS Output Signal Swing . . . . . . . . . . .
3.8.8 LVCMOS Output Polarity . . . . . . . . . . . . .
3.8.9 Output Enable/Disable . . . . . . . . . . . . . .
3.8.10 Output Disable During LOL . . . . . . . . . . . .
3.8.11 Output Disable During XAXB_LOS . . . . . . . . .
3.8.12 Output Driver State When Disabled . . . . . . . . .
3.8.13 Synchronous/Asynchronous Output Disable . . . . . .
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Rev. 1.1 | 2
3.8.14 Output Divider (R) Synchronization .
3.9 Power Management .
3.11 Serial Interface
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3.10 In-Circuit Programming .
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.22
.22
.22
.22
.22
.22
3.12 Custom Factory Preprogrammed Parts .
3.13 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . .
4. Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . . . . 25
39
5. Electrical Specifications
6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . .
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8. Typical Operating Characteristics (Jitter and Phase Noise)
9. Pin Descriptions
10. Package Outlines
. . . . . . . . . . . . . 42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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.49
.50
10.1 Si5347 9x9 mm 64-QFN Package Diagram .
10.2 Si5346 7x7 mm 44-QFN Package Diagram .
11. PCB Land Pattern
12. Top Marking
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
silabs.com
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Rev. 1.1 | 3
Si5347/46 Rev D Data Sheet
Feature List
1. Feature List
The Si5347/46-D features are listed below:
• Four or two DSPLLs to synchronize to multiple inputs
• Generates any combination of output frequencies from any in-
put frequency
• Ultra low jitter:
• 95 fs typ (12 kHz – 20 MHz)
• Input frequency range:
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: up to 720 MHz
• LVCMOS: up to 250 MHz
• Flexible crosspoints route any input to any output clock
• Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz
to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or manual
•
•
•
•
•
•
Locks to gapped clock inputs
Automatic free-run and holdover modes
Fastlock feature for low nominal bandwidths
Glitchless on-the-fly DSPLL frequency changes
DCO mode: as low as 0.01 ppb steps per DSPLL
Core voltage:
• V
DD
: 1.8 V ±5%
• V
DDA
: 3.3 V ±5%
• Independent output clock supply pins: 3.3, 2.5, or 1.8 V
• Output-output skew:
• Using same DSPLL: 65 ps (Max)
• Serial interface: I
2
C or SPI
•
•
•
•
•
•
In-circuit programmable with non-volatile OTP memory
ClockBuilder Pro
software simplifies device configuration
Si5347: Quad DSPLL, 64-QFN 9×9 mm
Si5346: Dual DSPLL, 44-QFN 7×7 mm
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
silabs.com
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Rev. 1.1 | 4
Si5347/46 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si5347/46 Ordering Guide
Ordering Part Number
Si5347A-D-GM
1,2
Si5347B-D-GM
1,2
Si5347C-D-GM
1,2
Si5347D-D-GM
1,2
Si5346A-D-GM
1,2
Si5346B-D-GM
1,2
Si5347-D-EVB
Si5346-D-EVB
—
—
—
—
2
4
4
Number Of
DSPLLs
4
Number of
Outputs
8
Output Clock
Frequency Range
0.0001 to 720 MHz
0.0001 to 350 MHz
0.0001 to 720 MHz
0.0001 to 350 MHz
0.0001 to 720 MHz
0.0001 to 350 MHz
—
—
44-Lead 7x7
QFN
Evaluation
Board
—
—
—
—
Package
64-Lead 9x9
QFN
RoHS-6,
Pb-Free
Yes
Temp Range
–40 to 85 °C
Notes:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the
ClockBuilder Pro
software.
Part number format is: Si5347A-Dxxxxx-GM or Si5346A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing
the pre-programmed configuration.
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock
family
member (7, 6)
g = Device
grade
(A, B, C, D)
Product
Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
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Rev. 1.1 | 5
