SPE1225
5-Line ESD Protection Array
DESCRIPTION
The SPE1225 are designed by TVS array that is to protect
sensitive electronics from damage or latch-up due to ESD.
They are designed for use in applications where board
space is at a premium. SPE1225 will protect up to five
lines, and may be used on lines where the signal polarities
swing above and below ground.
SPE1225 offer desirable characteristics for board level
protection including fast response time, low operating and
clamping voltage, and no device degradation.
SPE1225 may be used to meet the immunity requirements
of IEC 61000-4-2, level 4. The small SOT-363 package
makes them ideal for use in portable electronics such as
cell phones, PDA’s, notebook computers, and digital
cameras.
APPLICATIONS
Cellular Handsets and Accessories
Cordless Phone
PDA
Notebooks and Handhelds
Portable Instrumentation
Digital Cameras
MP3 Player
FEATURES
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Protects five I/O lines
Working voltage: 12V
Low leakage current
Low operating and clamping voltages
PIN CONFIGURATION ( SOT-363 / SC-70 )
PART MARKING
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SPE1225
5-Line ESD Protection Array
ORDERING INFORMATION
Part Number
Package
Part
Marking
E5YW
E5YW
SPE1225S36RG
SOT-363
SPE1225S36RGB
SOT-363
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPE1225S36RG : Tape Reel ; Pb – Free
※
SPE1225S36RGB : Tape Reel ; Pb – Free ; Halogen – Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Peak Pulse Power ( tp = 8/20
μs
)
Maximum Peak Pulse Current ( tp = 8/20
μs
)
ESD per IEC 61000 – 4 – 2 (Air )
ESD per IEC 61000 – 4 – 2 (Contact )
Operating Junction Temperature
Storage Temperature Range
Lead Soldering Temperature
Symbol
Ppk
Ipp
Vpp
Vpp
T
J
T
STG
T
L
Typical
250
8
±15
±8
-55 ~ 125
-55 ~ 150
260 ( 10sec )
Unit
W
A
KV
KV
℃
℃
℃
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Reverse Stand – Off
Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
Cj
It = 1mA
V
RWM
= 12V , T=25℃
Ipp = 1A , tp = 8/20
μs
Ipp = 8A , tp = 8/20
μs
Between I/O Pin and GND
V
R
= 0V , f = 1MHz
16
13.3
1
19
25
20
Conditions
Min.
Typ
Max.
12
Unit
V
V
μA
V
V
pF
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SPE1225
5-Line ESD Protection Array
TYPICAL CHARACTERISTICS
Clamping Voltage (Ipp = 1A , tp = 8/20
μs
)
Clamping Voltage (Ipp = 8A , tp = 8/20
μs
)
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SPE1225
5-Line ESD Protection Array
TYPICAL CHARACTERISTICS
Fig 1 : Junction Capacitance V.S Reverse Voltage Applied
Fig 2 : Peak Plus Power V.S Exponential Plus Duration
Fig 3 : Clamp Voltage V.S Peak Pulse Current
Fig 4 : Forward Voltage Drop V.S Peak Forward
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SPE1225
5-Line ESD Protection Array
APPLICATION NOTE
Device Connection for Protection of Five Data Lines
SPE1225 is designed to protect up to five data lines. The device is connected as follows:
1. The TVS protection of five I/O lines is achieved by connecting pins 1, 3, 4, 5, and 6 to the data lines. Pin 2 is
connected to ground. The ground connection should be made directly to the ground plane for best results. The
path length is kept as short as possible to reduce the effects of parasitic inductance.
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the input terminals or connectors to restrict transient coupling.
2. Minimize the path length between the TVS and the protected line.
3. Minimize all conductive loops including power and ground loops.
4. The ESD transient return path to ground should be kept as short as possible.
5. Never run critical signals near board edges.
6. Use ground planes whenever possible.
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