SPN4850
N-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPN4850 is the N-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application , notebook computer power management and
other battery powered circuits where high-side
switching .
FEATURES
60V/7.2A,R
DS(ON)
= 27mΩ@V
GS
= 10V
60V/6.8A,R
DS(ON)
= 32mΩ@V
GS
= 4.5V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOP – 8P package design
APPLICATIONS
DC/DC Converter
Load Switch
PIN CONFIGURATION(SOP – 8P)
PART MARKING
2011/10 /04
Ver.2
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SPN4850
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
ORDERING INFORMATION
Part Number
SPN4850S8RG
SPN4850S8RGB
Symbol
S
S
S
G
D
D
D
D
Description
Source
Source
Source
Gate
Drain
Drain
Drain
Drain
Package
SOP- 8P
SOP- 8P
Part
Marking
SPN4850
SPN4850
※
SPN4850S8RG : 13” Tape Reel ; Pb – Free
※
SPN4850S8RGB : 13” Tape Reel ; Pb – Free ; Halogen -Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Avalanche Current
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
AS
P
D
T
J
T
STG
R
θJA
Typical
60
±20
7.2
6.8
40
15
2.5
1.6
-55/150
-55/150
80
Unit
V
V
A
A
A
W
℃
℃
℃/W
2011/10 /04
Ver.2
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SPN4850
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=250uA
V
GS(th)
V
DS
=V
GS
,I
D
=250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DD
=30V,R
L
=30Ω
I
D
≡1.0A,V
GEN
=10V
R
G
=6Ω
V
DS
=30V
GS
=0V
f=1MHz
V
DS
=0V,V
GS
=±20V
V
DS
=48V,V
GS
=0V
V
DS
=48V,V
GS
=0V
T
J
=55℃
V
DS
≥5V,V
GS
=10V
V
GS
= 10V,I
D
=7.2A
V
GS
=4.5V,I
D
=6.8A
V
DS
=15V,I
D
=6.2A
I
S
=1.7A,V
GS
=0V
60
1.0
3.0
±100
1
5
25
0.023
0.027
25
0.8
25
4.2
5.3
950
180
115
10
10
25
12
20
20
50
25
1400
0.027
0.032
1.2
30
V
nA
uA
A
Ω
S
V
V
DS
=30V,V
GS
=10V
I
D
= 6A
nC
pF
nS
2011/10 /04
Ver.2
Page 3
SPN4850
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2011/10 /04
Ver.2
Page 4
SPN4850
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2011/10 /04
Ver.2
Page 5
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