SPN4900
N-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPN4900 is the Dual N-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application , notebook computer power management and
other battery powered circuits where high-side
switching .
FEATURES
60V/5.3A,R
DS(ON)
= 118mΩ@V
GS
= 10V
60V/4.7A,R
DS(ON)
= 125mΩ@V
GS
= 4.5V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOP – 8P package design
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
PIN CONFIGURATION(SOP – 8P)
PART MARKING
2008/ 11/ 10
Ver.1
Page 1
SPN4900
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Symbol
S1
G1
S2
G2
D2
D2
D1
D1
Description
Source 1
Gate 1
Source 2
Gate 2
Drain 2
Drain 2
Drain 1
Drain 1
ORDERING INFORMATION
Part Number
SPN4900S8RGB
Package
SOP- 8P
Part
Marking
SPN4900
※
SPN4546S8RGB 13” Tape Reel ; Pb – Free ; Halogen – Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Avalanche Current
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
AS
P
D
T
J
T
STG
R
θJA
Typical
60
±20
Unit
V
V
A
A
A
W
℃
℃
℃/W
4.2
3.2
20
11
2.5
1.6
-55/150
-55/150
80
2008/ 11/ 10
Ver.1
Page 2
SPN4900
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=250uA
V
GS(th)
V
DS
=V
GS
,I
D
=250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DD
=30V,R
L
=8.8Ω
I
D
≡3.4A,V
GEN
=10V
R
G
=1Ω
V
DS
=15,V
GS
=0V
f=1MHz
V
DS
=0V,V
GS
=±20V
V
DS
=60V,V
GS
=0V
V
DS
=60V,V
GS
=0V
T
J
=85℃
V
DS
≥5V,V
GS
=10V
V
GS
= 10V,I
D
=5.3A
V
GS
=4.5V,I
D
=4.7A
V
DS
=15V,I
D
=4.3A
I
S
=1.7A,V
GS
=0V
60
0.5
1.5
±100
1
5
25
0.110
0.115
15
0.8
15
2.5
2.6
675
80
40
10
15
25
12
20
25
35
20
0.118
0.125
1.2
20
V
nA
uA
A
Ω
S
V
V
DS
=30V,V
GS
=10V
I
D
= 4.3A
nC
pF
nS
2008/ 11/ 10
Ver.1
Page 3
SPN4900
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2008/ 11/ 10
Ver.1
Page 4
SPN4900
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2008/ 11/ 10
Ver.1
Page 5
电子工程世界
