SPP4931
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP4931 is the Dual P-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application , notebook computer power management and
other battery powered circuits where high-side
switching .
FEATURES
-20V/-8.5A,R
DS(ON)
= 20mΩ@V
GS
=-4.5V
-20V/-8.0 A,R
DS(ON)
= 25mΩ@V
GS
=-2.5V
-20V/-5.0 A,R
DS(ON)
= 35mΩ@V
GS
=-1.8V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOP-8P package design
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
PIN CONFIGURATION(SOP – 8P)
PART MARKING
2010/03/20
Ver.2
Page 1
SPP4931
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
ORDERING INFORMATION
Part Number
SPP4931S8RG
SPP4931S8RGB
Symbol
S1
G1
S2
G2
D2
D2
D1
D1
Description
Source 1
Gate 1
Source 2
Gate 2
Drain 2
Drain 2
Drain 1
Drain 1
Package
SOP- 8P
SOP- 8P
Part
Marking
SPP4931
SPP4931
※
SPP4931S8RG : 13” Tape Reel ; Pb – Free
※
SPP4931S8RGB : 13” Tape Reel ; Pb – Free ; Halogen - Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
-20
±12
Unit
V
V
A
A
A
W
℃
℃
℃/W
-8.5
-7.0
-30
-2.3
2.8
1.8
-55/150
-55/150
70
2010/03/20
Ver.2
Page 2
SPP4931
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=-250uA
V
GS(th)
V
DS
=V
GS
,I
D
=-250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±12V
V
DS
=-16V,V
GS
=0V
V
DS
=-20V,V
GS
=0V
T
J
=55℃
V
DS
≦-5V,V
GS
=-4.5V
V
GS
=- 4.5V,I
D
=-8.5A
V
GS
=- 2.5V,I
D
=-8.0A
V
GS
=- 1.8V,I
D
=-5.0A
V
DS
=-5.0V,I
D
=-10.0A
I
S
=-2.5A,V
GS
=0V
-20
-0.35
-0.9
±100
-1
-10
-20
0.016
0.020
0.028
36
-0.8
0.020
0.025
0.035
-1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=-10V,V
GS
=-5.0V
I
D
≡-10.0A
30
4.5
8.0
2670
520
480
25
45
nC
V
DS
=-10V,V
GS
=0V
f=1MHz
pF
40
70
240
115
ns
V
DD
=-10V,R
L
=15Ω
I
D
≡-1.0A,V
GEN
=-4.5V
R
G
=6Ω
45
145
70
2010/03/20
Ver.2
Page 3
SPP4931
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2010/03/20
Ver.2
Page 4
SPP4931
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2010/03/20
Ver.2
Page 5
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