SPP9433W
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP9433W is the P-Channel logic enhancement
mode power field effect transistors are produced using
high cell density, DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits, and low in-line power loss are needed in a very
small outline surface mount package.
FEATURES
-30V/-6A,R
DS(ON)
= 42mΩ@V
GS
=-10V
-30V/-3 A,R
DS(ON)
= 78mΩ@V
GS
=-4.5V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOP-8P package design
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
LCD Display inverter
PIN CONFIGURATION(SOP – 8P)
PART MARKING
2011/09/29
Ver.2
Page 1
SPP9433W
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
ORDERING INFORMATION
Part Number
SPP9433WS8RGB
Symbol
S
S
S
G
D
D
D
D
Description
Source
Source
Source
Gate
Drain
Drain
Drain
Drain
Package
SOP- 8P
Part
Marking
SPP9433W
※
SPP9433WS8RGB : 13” Tape Reel ; Pb – Free ; Halogen - Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
-30
±20
-6
-4
-12
-6
2.08
-55/150
-55/150
60
Unit
V
V
A
A
A
W
℃
℃
℃/W
2011/09/29
Ver.2
Page 2
SPP9433W
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=-250uA
V
GS(th)
V
DS
=V
GS
,I
D
=-250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±20V
V
DS
=-24V,V
GS
=0V
V
DS
=-24V,V
GS
=0V
T
J
=55℃
V
DS
≦-5V,V
GS
=-10V
V
GS
=- 10V,I
D
=-6A
V
GS
=- 4.5V,I
D
=-3A
V
DS
=-10.0V,I
D
=-6A
I
S
=-6A,V
GS
=0V
-30
-1.0
-2.5
±100
-1
-5
-6
0.035
0.065
6
0.042
0.078
-1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=-20V, V
GS
=-4.5V
I
D
=-6A
6.4
2.7
3.1
650
270
104
9
16
21
22
pF
nC
V
DS
=-24V,V
GS
=0V
f=1MHz
V
DD
=-12V, I
D
=-5.0A,
V
GEN
=-10V
R
G
=3.3Ω
ns
2011/09/29
Ver.2
Page 3
SPP9433W
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
Fig. 1 Typical Output Characteristics
Fig. 2 On-Resistance vs. Gate Voltage
Fig. 3 Forward characteristics of Diodes
Fig. 4 Gate Charge Characteristics
Fig. 5 Vgs vs. Junction Temperature
Fig. 6 On-Resistance vs Junction Temp
2011/09/29
Ver.2
Page 4
SPP9433W
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
Fig. 7 Typical Capacitance Characteristics
Fig. 8 Maximum Safe Operation Area
Fig. 9 Effective Transient Thermal Impedance
Fig. 10 Switching Time Waveform
Fig. 11 Unclamped Inductive Waveform
2011/09/29
Ver.2
Page 5
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