UC3842/43/44/45
CURRENT MODE
PWM
CONTROLLER
DESCRIPTION
The UC3842/UC3843/UC3844/UC3845 are fixed frequency current mode PWM controller.
They are specially designed for OFF−Line and DC to DC converter applications with
a minimal external components. Internally implemented circuits include a trimmed
oscillator for precise duty cycle control, a temperature compensated reference, high
gain error amplifier, current sensing comparator, and a high current totem pole output
ideally suited for driving a power MOSFET. Protection circuitry includes built under
voltage lockout and current limiting.
The UC3842, UC3844 have UVLO thresholds of 16 V (on) and 10 V (off).
The corresponding thresholds for the UC3843, UC3845 are 8.4V (on) and 7.6V (off).
The UC3842, UC3843 can operate within 100% duty cycle.
The UC3844, UC3845 can operate within 50% duty cycle.
PIN CONNECTION
(TOP VIEW)
FEATURES
•
•
•
•
Low Start-Up and Operating Current
High Current Totem Pole Output
Under voltage Lockout With Hysteresis
Operating Frequency Up To 500KHz
BLOCK DIAGRAM
(toggle flip flop used only in UC3844, UC3845)
Absolute Maximum Ratings
Characteristic
Supply Voltage (low impedance source)
Output Current
Input Voltage (Analog Inputs pins 2,3)
Error Amp Output Sink Current
Power Dissipation (T
A
=25 C)
Storage Temperature Range
Lead Temperature (soldering 5 sec.)
0
Symbol
V
CC
I
O
V
I
I
SINK (E.A)
P
O
Tstg
T
L
Value
30
±1
−0.3
to 5.5
10
1
-65 to150
260
Unit
V
A
V
mA
W
o
o
C
C
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2018 JUN
UC3842/43/44/45
Electrical characteristics (*V
CC
=15V, R
T
=10kΩ, C
T
=3.3nF, T
A
=0
0
C to +70
0
C, unless otherwise specified)
Characteristics
Reference Section
Reference Output Voltage
Line Regulation
Load Regulation
Short Circuit Output Current
Oscillator Section
Oscillation Frequency
Frequency Change with Voltage
Oscillator Amplitude
Error Amplifier Section
Input Bias Current
Input Voltage
Open Loop Voltage Gain
Unity Gain Bandwidth
Power Supply Rejection Ratio
Output Sink Current
Output Source Current
High Output Voltage
Low Output Voltage
Current Sense Section
Gain
Maximum Input Signal
Supply Voltage Rejection
Input Bias Current
Output Section
Low Output Voltage
High Output Voltage
Rise Time
Fall Time
Undervoltage Lockout Section
Start Theshold
Min. Operating Voltage
(After Turn On)
PWM Section
Max. Duty Cycle
Min. Duty Cycle
Total Standby Current
Start−Up Current
Operating Supply Current
I
ST
I
CC (OPR)
UC3842/43/44/45
V
pin3
= V
pin2
= 0V
30
0.17
13
38
0.3
17
mA
V
D
(MAX)
D
(MAX)
UC3842,UC3843
UC3844,UC3845
95
47
97
48
100
50
0
%
V
TH(ST)
V
OPR(min)
UC3842,UC3844
UC3843,UC3845
UC3842,UC3844
UC3843,UC3845
14.5
7.8
8.5
7.0
16.0
8.4
10
7.6
17.5
9.0
11.5
8.2
V
V
V
OL
V
OH
t
R
t
F
I
SINK
= 20 mA
I
SINK
= 200 mA
I
SINK
= 20 mA
I
SINK
= 200 mA
T
J
= 25°C, C
L
= 1nF (Note 3)
T
J
= 25°C, C
L
= 1nF (Note 3)
13
12
0.08
1.4
13.5
13.0
45
35
150
150
nS
0.4
2.2
V
G
V
V
I(MAX)
SVR
I
BIAS
(Note 1 & 2)
V
pin1
= 5V (Note1)
12V
≤
V
CC
≤
25 V (Note 1)
V
pin3
= 3V
2.85
0.9
3.0
1.0
70
-3.0
-10
3.15
1.1
V/V
V
dB
µA
I
BIAS
V
I(E.A)
A
VOL
UGBW
PSRR
I
SINK
I
SOURCE
V
OH
V
OL
V
FB
=3V
V
pin1
= 2.5V
2V
≤
V
0
≤
4V
T
j
=25 C, Note 3
12V
≤
V
CC
≤
25 V
V
pin2
= 2.7V, V
pin1
= 1.1V
V
pin2
= 2.3V, V
pin1
= 5V
V
pin2
= 2.3V, R
L
= 15KΩ to GND
V
pin2
= 2.7V, R
L
= 15KΩ to PIN 8
0
Symbol
V
REF
∆V
REF
∆V
REF
I
SC
f
∆f/∆V
CC
V
(OSC)
Test Condition
T
J
= 25°C, I
REF
= 1 mA
12V
≤
V
CC
≤
25 V
1 mA
≤
I
REF
≤
20mA
T
A
= 25°C
T
J
= 25°C
12V
≤
V
CC
≤
25 V
(peak to peak)
Min
4.9
Typ
5.0
6.0
6.0
-100
Max
5.1
20
25
-180
57
1.0
Unit
V
mV
mA
KHz
%
V
47
52
0.05
1.6
-0.1
-2
2.58
µA
V
dB
MHz
dB
mA
mA
2.42
65
0.5
60
2
-0.5
5.0
2.5
90
0.6
70
7
-1.0
6.0
0.8
1.1
V
Zener Voltage
V
Z
I
CC
=25 mA
* Adjust V
CC
above the start threshold before setting it to 15V.
Note 1: Parameter measured at trip point of latch with V
pin2
=0.
Note 2: Gain defined as A=∆V
pin1
/∆V
pin3
; 0
≤
V
pin3
≤
0.8V.
Note 3: These parameters, although guaranteed, are not 100% tested in production.
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UC3842/43/44/45
PIN FUNCTION
N
1
2
3
4
5
6
7
8
FUNCTION
COMP
V
FB
I
SENSE
R
T
/C
T
GROUND
OUTPUT
V
CC
V
ref
DESCRIPTION
This pin is the Error Amplifier output and is made for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply
output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this information to
terminate the output switch conduction.
The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor R
T
to V
ref
and capacitor C
T
to ground.
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sink
by this pin.
This pin is the positive supply of the integrated circuit.
This is the reference output. It provides charging current for capacitor C
T
through resistor R
T
.
APPLICATION INFORMATION
Figure 1. Error Amp Configuration
Figure 2. Under voltage Lockout
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2018 JUN
UC3842/43/44/45
Figure 3. Current Sense Circuit
Figure 4. Slope Compensation Techniques
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2018 JUN
UC3842/43/44/45
SCR must be selected for a holding current of less than 0.5mA.
The simple two transistor circuit can be used in place of the SCR as shown.
Figure 5. Latched Shutdown
Figure 6. Error Amplifier Compensation
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2018 JUN
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