UM3212
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
UM3212M8
MSOP8
UM3212DA
DFN8 2.1×1.6
General Description
The UM3212 is a dual bidirectional I
2
C-bus and SMBus voltage-level translator with an
enable(EN) input, and is operational from 1.0 V to 3.6 V (V
ref(1)
) and 1.8 V to 5.5 V(V
bias(ref)(2)
).
The UM3212 allows bidirectional voltage translations between 1.0 V and 5 V without the use of a
direction pin. The low ON-state resistance (R
on
) of the switch allows connections to be made with
minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and
SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data
flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state
exists between ports.
The UM3212 is not a bus buffer which provides both level translation and physically isolates the
capacitance to either side of the bus when both sides are connected. The UM3212 only isolates
both sides when the device is disabled and provides voltage level translation when active.
The UM3212 can also be used to run two buses, one at 400 kHz operating frequency and the other
at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100
kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is
running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because
of the delays added by the translator.
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic HIGH
levels on the translator’s bus. The UM3212 has a standard open-collector configuration of the
I
2
C-bus. The size of these pull-up resistors depends on the system, but each side of the translator
must have a pull-up resistor. The device is designed to work with Standard-mode, Fast-mode and
Fast-mode Plus I
2
C-bus devices in addition to SMBus devices. The maximum frequency is
dependent on the RC time constant, but generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on the
SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the voltage
set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply
voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a seamless translation between
higher and lower voltages selected by the user without the need for directional control. The
SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.
All channels have the same electrical characteristics and there is minimal deviation from one
output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the same time
protects less ESD-resistant devices.
Applications
I
2
C, SMBus and SPI Level Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
Cell-phone Cradles
Portable POS Systems
Portable Communication Devices
Low-Cost Serial Interfaces
Cell-Phones
GPS
Telecommunications Equipment
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UM3212
Features
2-bit bidirectional translator for SDA
and SCL lines in mixed-mode I
2
C-bus
applications
Standard-mode, Fast-mode, Fast-mode
Plus and HS-mode I
2
C-bus and SMBus
compatible
Less than 3.5ns maximum propagation
delay to accommodate Standard-mode
and Fast-mode I
2
C-bus devices and
multiple masters
Allows voltage level translation
between:
1.) 1.0V VREF1 and 1.8V, 2.5V, 3.3V
or 5V VREF2
2.) 1.2V VREF1 and 1.8V, 2.5V, 3.3V
or 5V VREF2
3.) 1.8V VREF1 and 3.3V or 5V
VREF2
4.) 2.5V VREF1 and 5V VREF2
5.) 3.3V VREF1 and 5V VREF2
Open-drain I
2
C-bus I/O ports (SCL1,
SDA1, SCL2 and SDA2)
Provides bidirectional voltage translation
with no direction pin
Low 3.0Ω ON-state connection between
input and output ports provides less signal
distortion
5V tolerant I
2
C-bus I/O ports to support
mixed-mode signal operation
High-impedance SCL1, SDA1, SCL2 and
SDA2 pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of
printed-circuit board trace routing
ESD protection exceeds 2000V HBM per
JESD22-A114,
200V
MM
per
JESD22-A115, and 1000V CDM per
JESD22-C101
Packages offered: MSOP8, DFN8
Pin Configurations
Top View
XX: Week Code
UM3212M8 MSOP8
GND
VREF1
SCL1
SDA1
1
2
3
4
8
EN
7 VREF2
6
5
SCL2
SDA2
M: Month Code
UM3212DA DFN8 2.1×1.6
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M
UM3212
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
Symbol
GND
VREF1
SCL1
SDA1
SDA2
SCL2
VREF2
EN
Function
Ground (0V).
Low-voltage side reference supply voltage for SCL1 and SDA1.
Serial clock, low-voltage side; connect to VREF1 through a pull-up
resistor.
Serial data, low-voltage side; connect to VREF1 through a pull-up
resistor.
Serial data, high-voltage side; connect to VREF2 through a pull-up
resistor.
Serial clock, high-voltage side; connect to VREF2 through a pull-up
resistor.
High-voltage side reference supply voltage for SCL2 and SDA2.
Switch enable input; connect to VREF2 and pull-up through a high
resistor.
Ordering Information
Part Number
UM3212M8
UM3212DA
Packaging Type
MSOP8
DFN8 2.1×1.6
Marking Code
3212
3212
Shipping Qty
3000pcs/13Inch
Tape & Reel
3000pcs/7Inch
Tape & Reel
Absolute Maximum Ratings (Note 1)
Over operating free-air temperature range (unless otherwise noted)
Symbol
Parameter
V
ref(1)
Reference Voltage (1)
V
bias(ref)(2)
Reference Bias Voltage (2)
V
I
V
I/O
I
ch
Input Voltage
Voltage on an input/output pin
Channel Current (DC)
Value
-0.5 to +6
-0.5 to +6
-0.5(Note 2) to +6
-0.5(Note 2) to +6
+128
Unit
V
V
V
V
mA
I
IK
Input Clamp Current
-50
mA
V
I
＜0V
T
stg
Storage Temperature Range
-65 to +150
°C
Note 1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Note 2: The input and input/output negative voltage ratings may be exceeded if the input and
input/output clamp current ratings are observed.
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UM3212
Recommended Operating Conditions
Symbol
V
I/O
V
ref(1)
(Note 3)
V
bias(ref)(2)
(Note 3)
V
I(EN)
I
sw(pass)
T
amb
Parameter
Voltage on an input/output
pin
Reference Voltage (1)
Reference Bias Voltage (2)
Input Voltage on pin EN
Pass Switch Current
Ambient Temperature
Operating in free-air
-40
Conditions
SCL1, SDA1,
SCL2, SDA2
VREF1
VREF2
Min
0
0
0
0
Max
5
5
5
5
64
+85
Unit
V
V
V
V
mA
°C
Note 3：V
ref(1)
≤
V
bias(ref)(2)
−1
V for best results in level shifting applications.
Electrical Characteristics
T
amb
=
−40
°C to +85 °C, unless otherwise specified.
Symbol
V
IK
I
IH
C
i(EN)
C
io(off)
C
io(on)
Parameter
Input Clamping Voltage
HIGH-level
Input Current
Input Capacitance on
pin EN
Off-state input/output
capacitance
On-state input/output
capacitance
Conditions
I
I
=
−18
mA; V
I(EN)
= 0 V
V
I
= 5 V;
V
I(EN)
= 0 V
V
I
= 0 V or 3 V
SCLn, SDAn;
V
O
= 0 V or 3 V ; V
I(EN)
= 0V
SCLn, SDAn;
V
O
= 0 V or 3 V ; V
I(EN)
= 3V
SCLn, SDAn; EN = 4.5V
EN = 3V
(Note 6)
V
I
= 0;
EN = 2.3V
I
O
= 64mA
EN = 1.5V
SCLn, SDAn; EN = 4.5V
V
I
= 2.4V;
EN = 3V
I
O
= 15mA
SCLn, SDAn;
V
I
= 1.7V;
EN = 2.3V
I
O
= 15mA
13
10
8
2.0
2.4
3.1
11
4.6
50
50
12.2
12
5.0
6.0
8.0
32
7.5
80
80
Min
Typ(Note 4)
Max
-1.2
5
Unit
V
uA
pF
pF
pF
R
on
ON-state
resistance(Note 5)
Ω
Note 4：All typical values are at T
amb
= 25°C.
Note 5：Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2
terminals at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
Note 6：Guaranteed by design.
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UM3212
Switching Characteristics (translating down)
Over recommended operating free-air temperature range (unless otherwise noted). Values
guaranteed by design.
CL=50pF
CL=30pF
CL=15pF
Test
Symbol
Parameter
Conditions Min Max Min Max Min Max
V
I(EN)
= 3.3 V; V
IH
= 3.3 V; V
IL
= 0 V; V
M
=1.15V(see Figure 1).
LOW to HIGH
from
0
2.5
0
1.7
0
1.2
t
PLH
propagation
(input)
delay
SCL2 or
SDA2
HIGH to LOW
to (output)
t
PHL
propagation
0
2.5
0
2.0
0
1.3
SCL1 or
delay
SDA1.
V
I(EN)
=2.5V; V
IH
= 2.5 V; V
IL
= 0 V; V
M
= 0.75 V (see Figure 1).
LOW to HIGH
from
0
2.5
0
1.7
0
1.2
t
PLH
propagation
(input)
delay
SCL2 or
SDA2
HIGH to LOW
to (output)
t
PHL
propagation
0
3.0
0
2.0
0
1.3
SCL1 or
delay
SDA1.
Unit
ns
ns
ns
ns
Switching Characteristics (translating up)
Over recommended operating free-air temperature range (unless otherwise noted). Values
guaranteed by design.
CL=50pF
CL=30pF
CL=15pF
Test
Symbol
Parameter
Unit
Conditions Min Max Min Max Min Max
V
I(EN)
= 3.3 V; V
IH
= 2.3 V; V
IL
= 0 V; V
TT
= 3.3 V; V
M
= 1.15 V; R
L
= 300
Ω(see
Figure 1).
LOW to HIGH
from
0
2.35
0
1.5
0
1.0
ns
t
PLH
propagation
(input)
delay
SCL1 or
SDA1
HIGH to LOW
to (output)
t
PHL
propagation
0
3.35
0
2.25
0
1.4
ns
SCL2 or
delay
SDA2.
V
I(EN)
=2.5V; V
IH
= 1.5 V; V
IL
= 0 V; V
TT
= 2.5 V; V
M
= 0.75 V; R
L
= 300
Ω
(see Figure 1).
LOW to HIGH
from
0
2.35
0
1.5
0
1.0
ns
t
PLH
propagation
(input)
delay
SCL1 or
SDA1
HIGH to LOW
to (output)
t
PHL
propagation
0
3.5
0
2.5
0
1.5
ns
SCL2 or
delay
SDA2.
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