UM5202EEDF
Dual Channel Low Capacitance ESD Protection Array
UM5202EEDF SOT143
General Description
UM5202EEDF is surge rated diode arrays designed to protect high speed data interfaces. This
series has been specifically designed to protect sensitive components which are connected to data
and transmission lines from over-voltage caused by ESD (electrostatic discharge).
The unique design incorporates surge rated, low capacitance steering diodes and a TVS diode in a
single package. During transient conditions, the steering diodes direct the transient to either the
positive side of the power supply line or to ground. The internal TVS diode prevents over-voltage
on the power line, protecting any downstream components.
The low capacitance array configuration allows the user to protect two high-speed data or
transmission lines. The low inductance construction minimizes voltage overshoot during high
current surges. This device is optimized for ESD protection of portable electronics. They may be
used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ± 8kV
contact discharge).
Applications
USB 2.0
USB OTG
Monitors and Flat Panel
Displays digital Visual Interface (DVI)
High-Definition Multimedia Interface
(HDMI)
SIM Ports IEEE 1394 Firewire Ports
Features
Transient protection for high-speed data lines
to
IEC 61000-4-2 (ESD) ± 15kV (air), ± 8kV
(contact)
Array of surge rated diodes with internal
TVS Diode
Protects two I/O lines & power line
Low capacitance (<2pF) for high-speed
interfaces
No insertion loss to 2.0GHz
Low leakage current and clamping voltage
Low operating voltage: 5.0V
Solid-state silicon-avalanche technology
Pin Configurations
Top View
4
PIN4
PIN1
3
U2A
PIN1
PIN2
PIN3
2
WK: Week Code
UM5202EEDF
SOT143
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UM5202EEDF
Ordering Information
Part Number
UM5202EEDF
Working
Voltage
5.0V
Packaging Type
SOT143
Channel
2
Marking
Code
U2A
Shipping Qty
3000pcs /7Inch
Tape & Reel
Absolute Maximum Ratings
Peak Pulse Power (tp = 8/20µS)
Peak Pulse Current (tp = 8/20µS )
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
P
pk
I
PP
V
ESD
T
J
T
STG
150
6
±15
±8
-55 to +125
-55 to +150
Watts
A
kV
°C
°C
Electrical Characteristics
（Note
1）
PARAMETER
Reverse Stand-Off
Voltage
Reverse Breakdown
Voltage
Reverse Leakage
Current
Clamping Voltage
Clamping Voltage
SYMBOL
V
RWM
V
BR
I
R
V
C
V
C
It = 1mA, Pin 4 to Pin1
V
RWM
= 5V, T=25°C,
Pin4 to Pin1
I
PP
= 1A, 8/20µS,
Any pin to pin1
I
PP
= 6A, 8/20µS,
Any pin to pin1
V
R
= 0V, f = 1MHz,
Any I/O pin to pin1
V
R
= 0V, f = 1MHz ,
Between I/O pins
V
R
= 0V, f = 1MHz,
Pin4 to pin1
V
R
= 2.5V, f = 1MHz,
Pin4 to pin1
Pin1to Pin4
Pin1 to I/O Pin
Pin4 to I/O Pin
Note 1: I/O pins are pin 2, 3.
6.0
2
15
25
2
1
60
40
40
160
45
TEST CONDITIONS
MIN TYP MAX UNIT
5.0
V
V
µA
V
V
pF
pF
pF
pF
ns
ns
ns
Junction
Capacitance
C
j
Reverse Recovery
Time
Trr
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UM5202EEDF
Applications Information
Device Connection Options for Protection of two High-Speed Data Lines
This device is designed to protect data lines by clamping them to a fixed reference. When the
voltage on the protected line exceeds the reference voltage the steering diodes are forward biased,
conducting the transient current away from the sensitive circuitry. Data lines are connected at pins
2, 3. Pin 1 should be connected directly to a ground plane. The path length is kept as short as
possible to minimize parasitic inductance. The positive reference is connected at pin 4. The
options for connecting the positive reference are as follows:
1. To protect data lines and the power line, connect pin 4 directly to the positive supply rail (VCC).
In this configuration the data lines are referenced to the supply voltage. The internal TVS diode
prevents over-voltage on the supply rail.
2. In applications where the supply rail does not exit the system, the internal TVS may be used as
the reference. In this case, pin 4 is not connected. The steering diodes will begin to conduct when
the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop).
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte
tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads
is small compared to the solder paste volume that is placed on the land pattern of the PCB, the
reflow profile will be determined by the requirements of the solder paste. Therefore, these devices
are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other
lead-free compositions, matte tin does not have any added alloys that can cause degradation of the
solder joint.
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UM5202EEDF
Package Information
UM5202EEDF SOT143
Outline Drawing
Symbol
A
A1
A2
b
b2
C
D
E
E1
e
e1
L1
L
DIMENSIONS
MILLIMETERS
INCHES
Min
Max
Min
Max
0.763
1.220
0.031
0.049
0.013
0.150
0.001
0.006
0.750
1.070
0.030
0.043
0.300
0.510
0.012
0.020
0.760
0.930
0.030
0.037
0.080
0.200
0.003
0.008
2.800
3.040
0.112
0.122
2.200
2.640
0.088
0.211
1.200
1.400
0.048
0.056
1.920BSC
0.077BSC
0.200BSC
0.008BSC
0.540REF
0.022
0.400
0.600
0.016
0.024
Land Pattern
NOTES:
1. Compound dimension: 2.90×1.30;
2. Unit: mm;
3. General tolerance ±0.05mm unless otherwise specified;
4. The layout is just for reference.
Tape and Reel Orientation
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UM5202EEDF
IMPORTANT NOTICE
The information in this document has been carefully reviewed and is believed to be
accurate. Nonetheless, this document is subject to change without notice. Union assumes
no responsibility for any inaccuracies that may be contained in this document, and makes
no commitment to update or to keep current the contained information, or to notify a
person or organization of any update. Union reserves the right to make changes, at any
time, in order to improve reliability, function or design and to attempt to supply the best
product possible.
Union Semiconductor, Inc
Add: 2F, No. 3, Lane 647 Songtao Road, Shanghai 201203
Tel: 021-51093966
Fax: 021-51026018
Website: www.union-ic.com
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