DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3778
10600 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners and so on.
FEATURES
• Valid photocell
• Photocell size
• Line spacing
• Color filter
• Resolution
: 10600 pixels
×
3
: 4
×
4
µ
m
2
: 48
µ
m (12 lines) Red line-Green line, Green line-Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•hour)
: 48 dot/mm A4 (210
×
297 mm) size (shorter side)
1200 dpi US letter (8.5”
×
11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Power supply
: 5 MHz MAX.
: +12 V
Voltage amplifiers
• Photocell's pitch : 4
µ
m
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
µ
PD3778CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14374EJ2V0DS00 (2nd edition)
Date published October 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
µ
PD3778
BLOCK DIAGRAM
V
OD
29
GND
1
GND
16
φ
2
22
φ
1
19
CCD analog shift register
Transfer gate
V
OUT
1
(Blue)
30
........
Photocell
(Blue)
S10599
S10600
D14
D64
D65
D66
D67
S1
S2
18
φ
TG1
(Blue)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
V
OUT
2
(Green)
31
........
Photocell
(Green)
S10599
S10600
D14
D64
D65
D66
D67
S1
S2
17
φ
TG2
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
V
OUT
3
(Red)
32
........
Photocell
(Red)
S10599
S10600
D14
D64
D65
D66
D67
S1
S2
15
φ
TG3
(Red)
Transfer gate
CCD analog shift register
3
2
14
11
φ
CLB
φ
RB
φ
2
φ
1
2
Data Sheet S14374EJ2V0DS
µ
PD3778
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
•
µ
PD3778CY
Ground
Reset gate clock
Reset feed-through level
clamp clock
No connection
No connection
Internal connection
Internal connection
No connection
No connection
No connection
Shift register clock 1
Internal connection
Internal connection
Shift register clock 2
Transfer gate clock 3
(for Red)
Ground
GND
1
2
32
31
V
OUT
3
V
OUT
2
V
OUT
1
V
OD
NC
IC
IC
NC
NC
NC
Output signal 3 (Red)
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
No connection
Internal connection
Internal connection
No connection
No connection
No connection
Shift register clock 2
Internal connection
Internal connection
Shift register clock 1
Transfer gate clock 1
(for Blue)
Transfer gate clock 2
(for Green)
φ
RB
φ
CLB
NC
NC
IC
IC
NC
NC
NC
1
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Green
φ
1
IC
IC
Blue
Red
φ
2
IC
IC
10600
10600
φ
TG3
GND
10600
φ
2
φ
1
φ
TG1
φ
TG2
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Data Sheet S14374EJ2V0DS
3
µ
PD3778
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
4
µ
m
Blue photocell array
12 lines
(48
µ
m)
2
µ
m
2
µ
m
4
µ
m
Green photocell array
4
µ
m
Channel stopper
12 lines
(48
µ
m)
4
µ
m
Red photocell array
Aluminum
shield
4
Data Sheet S14374EJ2V0DS
µ
PD3778
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Note
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
RB
V
φ
CLB
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–25 to +60
–40 to +70
Unit
V
V
V
V
V
°C
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
RBH
V
φ
RBL
V
φ
CLBH
V
φ
CLBL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
f
φ
RB
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
5.0
0
V
φ
1H
Note
0
1.0
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
V
φ
1H
Note
+0.5
5.0
Unit
V
V
V
V
V
V
V
V
V
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
Data Sheet S14374EJ2V0DS
5
微控制器 MCU
