W5100S
(W5100S-L & W5100S-Q)
Version 1.0.0
http://www.wiznet.io/
© Copyright 2018 WIZnet Co., Ltd. All rights reserved.
W5100S
W5100S designed with Hardwired TCP/IP, WIZnet technology, is an embedded Internet
Controller Chip. W5100S supporting Full Hardwired, Ethernet MAC (Media Access Control), and
10Base-T/100Base-TX Ethernet PHY is Internet Connectivity One-chip Solution for Internet
Protocol (TCP/IP).
With W5100S, Host (User MCU) simply handles variety Internet Protocol such as IPv4, TCP,
UDP, ICMP, IGMP, ARP, PPPoE and etc. And W5100S supports each 8KB Memory for Transmit
and Receive to minimize using memory on Low-end level Host. Host also independently uses 4
Hardwired SOCKETs to develop vary Internet Applications in each Hardwired SOCKETs.
W5100S supports SPI and Parallel System BUS Interface for Host Interface. It also provides Low
Power / Low Heat design, WOL (Wake On LAN), Ethernet PHY Power Down Mode and etc.
W5100S is Low-cost chip that improves on W5100. Any Firmware using on W5100 can be used
on W5100S without any modification. Also, W5100S has 48 Pin LQFP & QFN Lead-Free
Package, smaller than W5100 for product miniaturization.
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W5100S Datasheet Version1.0.0
Features
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Support Hardwired Internet protocols
: TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE
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Support 4 independent SOCKETs simultaneously
Support SOCKET-less command
: ARP-Request, PING-Request
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Support Ethernet Power down mode & Main Clock gating for power save
Support Wake on LAN over UDP
Support Serial & Parallel Host Interface
: High Speed SPI (MODE 0/3), System Bus with 2 Address signal & 8bit Data
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Internal 16Kbytes Memory for TX/ RX Buffers
10BaseT/100BaseTX Ethernet PHY Integrated
Support Auto Negotiation (Full and half duplex, 10 and 100-based )
Support Auto-MDIX only when Auto-Negotiation mode
Not support IP Fragmentation
3.3V operation with 5V I/O signal tolerance
Network Indicator LEDs (Full/Half duplex, Link, 10/100 Speed, Active)
48 Pin LQFP & QFN Lead-Free Package (7x7mm, 0.5mm pitch)
Target Applications
W5100S is well-suited for many embedded applications, including:
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User product based on W5100 : No modify firmware
Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters
Serial-to-Ethernet: Access Controls, LED displays, Wireless AP relays, etc.
Parallel-to-Ethernet: POS / Mini Printers, Copiers
USB-to-Ethernet: Storage Devices, Network Printers
GPIO-to-Ethernet: Home Network Sensors
Security Systems: DVRs, Network Cameras, Kiosks
Factory, Building, Home Automations
Medical Monitoring Equipment
Embedded Servers
Internet of Thing (IoT) Devices
IoT Cloud Devices
W5100S Datasheet Version1.0.0
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Block Diagram
Figure 1 Block Diagram
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W5100S Datasheet Version1.0.0
Contents
1 PIN Description ........................................................................................ 11
1.1
2.1
PIN Description ............................................................................. 12
W5100S Registers........................................................................... 18
2.1.1
2.1.2
3.1
Common registers .................................................................... 18
SOCKET Registers .................................................................... 20
2 Memory Map ............................................................................................ 16
3 Register Descriptions ................................................................................. 22
Common Registers ......................................................................... 24
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10
3.1.11
3.1.12
3.1.13
3.1.14
3.1.15
3.1.16
3.1.17
3.1.18
3.1.19
3.1.20
3.1.21
3.1.22
3.1.23
3.1.24
3.1.25
3.1.26
3.1.27
3.1.28
3.1.29
MR (Mode Register) .................................................................. 24
GWR (Gateway IP Address Register) .............................................. 24
SUBR (Subnet Mask Register) ...................................................... 24
SHAR (Source Hardware Address Register) ...................................... 25
SIPR (Source IP Address Register) ................................................. 25
INTPTMR (Interrupt Pending Time Register) .................................... 25
IR (Interrupt Register)............................................................... 25
IMR (Interrupt Mask Register) ...................................................... 26
RTR (Retransmission Time Register) .............................................. 27
RCR (Retransmission Count Register) ............................................. 27
RMSR (RX Memory Size Register) .................................................. 27
TMSR (TX Memory Size Register) .................................................. 28
IR2 (Interrupt Register 2) ........................................................... 28
IMR2 (Interrupt Mask Register 2) .................................................. 29
PTIMER (PPP Link Control Protocol Request Timer Register) ................ 29
PMAGIC (PPP Link Control Protocol Magic number Register) ................. 29
UIPR (Unreachable IP Address Register) ......................................... 30
UPORTR (Unreachable Port Register) ............................................ 30
MR2 (Mode Register 2) .............................................................. 30
PHAR (Destination Hardware Address Register on PPPoE) .................... 32
PSIDR (Session ID Register on PPPoE) ............................................. 32
PMRUR (PPPoE Maximum Receive Unit Register) ............................... 32
PHYSR (PHY Status Register) ....................................................... 32
PHYRAR (PHY Register Address Register) ........................................ 33
PHYDIR (PHY Data Input Register) ................................................ 34
PHYDOR (PHY Data Output Register) ............................................. 34
PHYACR (PHY Access Control Register) .......................................... 34
PHYDIVR (PHY Division Register) .................................................. 34
PHYCR0 (PHY Control Register 0) ................................................. 34
W5100S Datasheet Version1.0.0
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FPGA/CPLD
