Powerline Modules
500Mbps Modules
The Single In-line Package (SIP) module is an IEEE1901 and
HomePlug AV based MAC/PHY/AFE Powerline Communications
(PLC) transceiver/modem.
The Module provides an integrated solution for Powerline
communications. The “Black Box” design requires no external
software and only a few external components to create a working
solution. Operate as a PHY or MAC is selectable via Pull up/down
resistor.
Communication is possible over any 2 wire system DC/AC or Dry
wire.
Key Features & Benefits
Based on Qualcomm Atheros AR7410/AR1500 chipset
Industrial Temperature Range -40°C – +85°C
Supports IEEE1901 HomePlug® AV Standard with data rates of
500Mbps
RGMII (0804-5000⬜50) or MII (0804-5000⬜51) (Host & PHY)
interface
Supports 4096/1024/256/64/16/8-QAM, QPSK, BPSK and
ROBO modulation schemes
128-bit AES Link Encryption with key management for secure
power line communications
Windowed OFDM with noise mitigation based on patented
line synchronization techniques improves data integrity in
noisy conditions
Dynamic channel adaptation and channel estimation
maximizes throughput in harsh channel conditions
Horizontal mounting configuration using standard 1.27mm
pin header (50 way)
Integrates core components necessary to add HomePlug AV
functionality to any embedded system at low cost
Designed to meet Class A conducted emissions EMC
standards for industrial applications
0804-5000⬜51 offers a MII interface and is compatible with
the existing 0804-5000-18/24 Modules
Models
Part Number
0804-5000A50
0804-5000A51
0804-5000E50
0804-5000E51
Temp Range
-40°C – +85°C Including Heatsink
-40°C – +85°C Including Heatsink
-40°C – +85°C Including Heatsink
-40°C – +85°C Including Heatsink
Interface
RGMII
MII (0804-5000-18/24 compatible)
RGMII
MII (0804-5000-18/24 compatible)
Market
US
US
EU
EU
Bel Modules
28 Turkey Court, Turkey Mill, Ashford Road
Maidstone ME14 5PP UK
[1]
© 2017 Bel Power Solutions, Inc.
+44 1622 757 395
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Rev E
Powerline Modules
500Mbps Module
Module Block Diagram
GPIO
LEDs
AND
CONFIG
M
A
RGMII
MII
C
P
H
Y
TX
DAC
BPF
PLC
COUPLER
ADC
AR1500
AR7410
FLASH
RAM
DC/DC
ZERO CROSS
DETECTOR
RX
BPF
RESET
SYS CLK
PLL
3.3V
DC
CLOCK
1.26V 2.5V 11.2V
* Dotted line signifies Modules External connectivity.
System Block Diagram
POWER
RESET
AC Mains
/
DC
or
Dry wire
PLC
COUPLER
RGMII/MII
PHY DEVICE
POWERLINE
MODULE
ZERRO CROSS
DETECTOR
PHY UTILITY
*
AC only
MDIO
OR
MAC
CONTROLLER
GPIO
The block diagram presents the Powerline module in a typical environment.
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Powerline Modules
500Mbps Module
Module Interface
Module connectivity is provided via a 50 way 1.27mm pitch gold pin header.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pin Name
MII
VDD
VSS
VDD
VSS
VNET_IO
TXRX+
TXRX-
VSS
RESERVED
[1]
RESERVED
[1]
RESET#
GPIO0
GPIO1
GPIO2
RESERVED
[1]
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO3
GPIO10
GPIO11
ZC_IN
MDIO
MDC
RESERVED
[1]
RESERVED
[1]
VSS
MRX_D0
MRX_D1
MRX_D2
MRX_D3
COL
MRX_CLK
Type
RGMII
PWR
PWR
PWR
PWR
PWR
I/O
I/O
PWR
-
-
I
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
MAC
/I
PHY
-
-
PWR
RD0
RD1
RD2
RD3
RESERVED
[2]
RXC
I
MAC
/O
PHY
I
MAC
/O
PHY
I
MAC
/O
PHY
I
MAC
/O
PHY
I
MAC
/O
PHY
I
MAC
/O
PHY
Description
+3.3V
Ground
+3.3V
Ground
+2.5V / +3.3V
Differential TXRX signal, connects to coupling transformer
Differential TXRX signal, connects to coupling transformer
Ground
Reserved pin
Reserved pin
Resets all IC logic when low
Strap: ENET_SEL[0]
Strap: ENET_SEL[1]; Push-button: Simple connect
Strap: ANEN; Push-button: Factory default
Reserved pin
Strap: SPEED_SEL[0]
Strap: MD_A3
Strap: CFG_SEL
Strap: MD_A4
Strap: MP_SEL; LED: Powerline Tx/Rx Link
Strap: ISODEF; LED: Ethernet Tx/Rx Link
Strap: BM_SEL
Strap: SPEED_SEL[1]; LED: Power
Zero-cross detection signal
Management Data Interface Data Line
Management Data Interface Clock Line
Reserved pin
Reserved pin
Ground
MII / RGMII: Receive Data Bits (MAC)
MII / RGMII: Receive Data Bits (MAC)
MII / RGMII: Receive Data Bits (MAC)
MII / RGMII: Receive Data Bits (MAC)
MII: Collision Detected
MII / RGMII: Receive Clock (MAC)
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Powerline Modules
500Mbps Module
Pin Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
MII
VSS
MRX_ERR
MRX_DV
MTX_D0
MTX_D1
MTX_D2
MTX_D3
CRS
MTX_CLK
MTX_EN
VSS
PHY_RST#
VSS
PHY_CLK
VSS
Type
RGMII
PWR
RESERVED
[2]
RX_CTL
TD0
TD1
TD2
TD3
RESERVED
[2]
TXC
TX_CTL
I
MAC
/O
PHY
I
MAC
/O
PHY
O
MAC
/I
PHY
O
MAC
/I
PHY
O
MAC
/I
PHY
O
MAC
/I
PHY
I
MAC
/O
PHY
MII:
I
MAC
/O
PHY
RGMII: O
MAC
/I
PHY
O
MAC
/I
PHY
PWR
O
PWR
O
PWR
Description
Ground
MII: Receive Error (MAC)
MII: Receive Data Valid (MAC)
RGMII: Receive control signal (MAC)
MII / RGMII: Transmit Data Bits (MAC)
MII / RGMII: Transmit Data Bits (MAC)
MII / RGMII: Transmit Data Bits (MAC)
MII / RGMII: Transmit Data Bits (MAC)
MII: Carrier Sense
MII: Transmit Clock (MAC)
RGMII: Transmit Clock (MAC)
MII: Transmit Enable (MAC)
RGMII: Transmit Control Signal (MAC)
Ground
Reset Ethernet PHY
Ground
Strap: DUPLEX; 25MHz Clock for Ethernet PHY
Ground
[1] Leave reserved pins disconnected
[2] Add pull down 10kΩ resistor
Ethernet interface
The Ethernet interface can be configured in MAC or PHY mode and depending on the module model either MII or RGMII
protocols are supported.
MAC or PHY mode
RGMII (0804-5000⬜50) or MII (0804-5000⬜51) protocol
In MAC mode, the SIP is configured to be an Ethernet MAC and to communicate to an external Ethernet PHY device. This
configuration is typical in an Ethernet Wall Adapter application. In PHY mode, the SIP is configured to be a Physical Medium
Dependent (PMD) or PHY controller. In this configuration, an external MAC controls the SIP; this configuration is typical in
an embedded application, such as a set-top box. Regardless of which mode is used, the SIP can be configured to use one of
below protocols:
MII (100 Mbps max) Complies with 802.3(u)
RGMII (1000 Mbps max) Supports RGMII v1.3 with internal 2ns delays
The MAC and PHY configurations support 10 and 100 Mbps in half and full-duplex, and 1000 Mbps in full duplex mode only.
When the RGMII interface is used, regardless of the speed, only full-duplex is supported. Flow control is supported in
half-duplex using “back-pressure” preamble assertion, and using pause packets in full-duplex mode. The Ethernet interface
includes the management data interface for MAC and PHY controller functions. The Ethernet MAC module implements a
standard Ethernet MAC function. The Ethernet MAC will be connected to an external Ethernet PHY function. The MAC
configuration provides bridging between Ethernet and PLC. The PHY configuration emulates Ethernet PHY functionality and
provides PLC connectivity to devices designed to communicate over an Ethernet physical network.
The Ethernet interface has separate transmit and receive packet buffering. When operating as a MAC the transmit FIFO is 2
KB and the receive FIFO is 16 KB. When operating as a PHY controller, the transmit FIFO is 16 KB and the receive FIFO is 2
KB.
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Powerline Modules
500Mbps Module
MII Bus Signals
Pin
Number
30
31
32
33
Pin Name
MRX_D0
MRX_D1
MRX_D2
MRX_D3
I/O
MAC Mode
Description
PHY Mode
Transmit Data Bits.
The PHY controller drives MRX_D[3:0] and the MAC core
receives MRX_D[3:0]. MRX_D[3:0] transition synchronously with respect to
MRX_CLK. For each MRX_CLK period in which MRX_DV is asserted,
MRX_D[3:0] is valid. MRX_D0 is the least-significant bit. The PHY controller tri-
states MRX_D[3:0] in isolate mode.
Collision Detected.
The PHY controller asserts COL when it detects a collision
on the medium. COL remains asserted while the collision condition persists.
COL signal transitions are not synchronous to either the MTX_CLK or the
MRX_CLK. The MAC core ignores the COL signal when operating in the full-
duplex mode. The PHY controller tri-states COL in isolate mode.
Receive Clock.
MRX_CLK is a continuous clock that provides the timing
reference for the transfer of the MRX_DV and MRX_D[3:0] signals from the PHY
controller to the MAC core. The PHY controller sources MRX_CLK. MRX_CLK
frequency is equal to 25% of the data rate of the received signal on the
Ethernet cable. The PHY controller tri-states MRX_CLK in isolate mode.
Receive Error.
The PHY controller asserts MRX_ERR high for one or more
MRX_CLK periods to indicate to the MAC core that an error (a coding error or
any error that the PHY is capable of detecting that is otherwise undetectable by
the MAC) was detected somewhere in the current frame. MRX_ERR transitions
synchronously with respect to MRX_CLK. While MRX_DV is de-asserted,
MRX_ERR has no effect on the MAC core. The PHY controller tri-states
MRX_ERR in isolate mode.
Receive Data Valid.
The PHY controller asserts MRX_DV to indicate to the MAC
core that it is presenting the recovered and decoded data bits on MRX_D[3:0]
and that the data on MRX_D[3:0] is synchronous to MRX_CLK. MRX_DV
transitions synchronously with respect to MRX_CLK. MRX_DV remains asserted
continuously from the first recovered nibble of the frame through the final
recovered nibble, and is de-asserted prior to the first MRX_CLK that follows the
final nibble. The PHY controller tri-states MRX_DV in isolate mode.
Transmit Data Bits.
The MAC core drives MTX_D[3:0] and the PHY controller
receives MTX_D[3:0]. MTX_D[3:0] transitions synchronously with respect to
MTX_CLK. For each MTX_CLK period in which MTX_EN is asserted, MTX_D[3:0]
is valid. MTX_D0 is the least-significant bit. The PHY controller ignores
MTX_D[3:0] in isolate mode.
Carrier Sense.
The PHY controller asserts CRS when either transmit or receive
medium is non-idle. The PHY de-asserts CRS when both transmit and receive
medium are idle. The PHY must ensure that CRS remains asserted throughout
the duration of a collision condition. The transitions on the CRS signal are not
synchronous to either the MTX_CLK or the MRX_CLK. The PHY controller tri-
states CRS in isolate mode.
Transmit Clock.
MTX_CLK is a continuous clock that provides a timing
reference for the transfer of the MTX_EN and MTX_D[3:0] signals from the
MAC core to the PHY controller. The PHY controller sources MTX_CLK. The
operating frequency of MTX_CLK is 25 MHz when operating at 100 Mbps and
2.5 MHz when operating at 10 Mbps. The PHY controller tri-states MTX_CLK in
isolate mode.
Transmit Enable.
A high assertion on MTX_EN indicates that the MAC core is
presenting nibbles to the PHY controller for transmission. The SIP MAC core
asserts MTX_EN with the first nibble of the preamble and keeps MTX_EN
asserted while all nibbles to be transmitted are presented to the MII. MTX_EN
is de-asserted prior to the first MTX_CLK following the final nibble of the frame.
MTX_EN transitions synchronously with respect to MTX_CLK. The PHY
controller ignores MTX_EN in isolate mode.
I
O
34
COL
I
O
35
MRX_CLK
I
O
37
MRX_ERR
I
O
38
MRX_DV
I
O
39
40
41
42
MTX_D0
MTX_D1
MTX_D2
MTX_D3
O
I
43
CRS
I
O
44
MTX_CLK
I
O
45
MTX_EN
O
I
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