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100328QIX

TTL to ECL Transceiver, 8 Func, True Output, ECL, PQCC28, 0.450 X 0.450 INCH, PLASTIC, MO-047, LCC-28

器件类别:模拟混合信号IC    驱动程序和接口   

厂商名称:Vishay(威世)

厂商官网:http://www.vishay.com

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器件参数
参数名称
属性值
厂商名称
Vishay(威世)
包装说明
QCCJ,
Reach Compliance Code
unknown
ECCN代码
EAR99
Is Samacsys
N
最大延迟
5.4 ns
接口集成电路类型
TTL TO ECL TRANSCEIVER
JESD-30 代码
S-PQCC-J28
长度
11.43 mm
位数
1
功能数量
8
端子数量
28
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出锁存器或寄存器
LATCH
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装形状
SQUARE
封装形式
CHIP CARRIER
座面最大高度
4.57 mm
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
表面贴装
YES
技术
ECL
温度等级
INDUSTRIAL
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
宽度
11.43 mm
Base Number Matches
1
文档预览
100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch
April 1989
Revised August 2000
100328
Low Power Octal ECL/TTL Bi-Directional Translator
with Latch
General Description
The 100328 is an octal latched bi-directional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of this translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. A HIGH on the latch
enable input (LE) latches the data at both inputs even
though only one output is enabled at the time. A LOW on
LE makes the 100328 transparent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is
2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100328 is designed with FAST
TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 k
pull-down resistors.
Features
s
Identical performance to the 100128 at 50% of the
supply current
s
Bi-directional translation
s
2000V ESD protection
s
Latched outputs
s
FAST TTL outputs
s
3-STATE outputs
s
Voltage compensated operating range
= −
4.2V to
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100328SC
100328PC
100328QC
100328QI
Package Number
M24B
N24E
V28A
V28A
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
E
0
–E
7
T
0
–T
7
OE
LE
DIR
Description
ECL Data I/O
TTL Data I/O
Output Enable Input
Latch Enable Input
Direction Control Input
All pins function at 100K ECL levels except for T
0
–T
7
.
FAST is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010219
www.fairchildsemi.com
100328
Connection Diagrams
24-Pin DIP/SOIC
Functional Diagram
28-Pin PLCC
Truth Table
OE
L
L
L
H
H
H
H
H
H
DIR
X
L
H
L
L
L
H
H
H
LE
L
H
H
L
L
H
L
L
H
ECL
Port
LOW
(Cut-Off)
Input
LOW
(Cut-Off)
L
H
X
L
H
Latched
L
H
L
H
X
Z
Input
(Note 1)(Note 3)
(Note 2)(Note 3)
(Note 1)(Note 4)
(Note 1)(Note 4)
(Note 2)(Note 4)
(Note 2)(Note 4)
(Note 2)(Note 4)
Note:
LE, DIR, and OE use ECL logic levels
TTL
Port
Z
Notes
Detail
Latched (Note 1)(Note 3)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don’t Care
Z
=
High Impedance
Note 1:
ECL input to TTL output mode.
Note 2:
TTL input to ECL output mode.
Note 3:
Retains data present before LE set HIGH.
Note 4:
Latch is transparent.
www.fairchildsemi.com
2
100328
Absolute Maximum Ratings
(Note 5)
Storage Temperature (T
STG
)
V
EE
Pin Potential to Ground Pin
V
TTL
Pin Potential to Ground Pin
ECL Input Voltage (DC)
ECL Output Current
(DC Output HIGH)
TTL Input Voltage (Note 6)
TTL Input Current (Note 6)
Voltage Applied to Output
in HIGH State
3-STATE Output
Current Applied to TTL
Output in LOW State (Max)
ESD (Note 7)
twice the rated I
OL
(mA)
65
°
C to
+
150
°
C
7.0V to
+
0.5V
0.5V to
+
6.0V
V
EE
to
+
0.5V
Recommended Operating
Conditions
Case Temperature (T
C
)
Commercial
Industrial
ECL Supply Voltage (V
EE
)
TTL Supply Voltage (V
TTL
)
0
°
C to
+
85
°
C
Maximum Junction Temperature (T
J
)
+
150
°
C
40
°
C to
+
85
°
C
5.7V to
4.2V
+
4.5V to
+
5.5V
50 mA
0.5V to
+
6.0V
30 mA to
+
5.0 mA
0.5V to
+
5.5V
Note 5:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 6:
Either voltage limit or current limit is sufficient to protect inputs.
Note 7:
ESD testing conforms to MIL-STD-883, Method 3015.
2000V
Commercial Version
TTL-to-ECL DC Electrical Characteristics
(Note 8)
V
EE
= −
4.2V to
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
°
C to
+
85
°
C, V
TTL
= +4.5V
to
+5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
OH
V
OL
Output HIGH Voltage
Output LOW Voltage
Cutoff Voltage
−2000
V
OHC
V
OLC
V
IH
V
IL
I
IH
I
IL
V
FCD
I
EE
Output HIGH Voltage
Corner Point HIGH
Output LOW Voltage
Corner Point LOW
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Breakdown Test
Input LOW Current
Input Clamp Diode Voltage
V
EE
Supply Current
−159
−169
−75
−75
mA
−700
−1.2
2.0
0
−1950
mV
−1025
−1830
−955
−1705
−870
−1620
mV
mV
Conditions
V
IN
=
V
IH(Max)
or V
IL(Min)
Loading with 50Ω to
2V
OE or DIR LOW,
V
IN
=
V
IH(Max)
or V
IL(Min)
,
Loading with 50Ω to
−2V
−1035
−1610
5.0
0.8
70
1.0
mV
mV
V
V
µA
mA
µA
V
V
IN
=
V
IH(Min)
or V
IL(Max)
Loading with 50Ω to
−2V
Over V
TTL
, V
EE
, T
C
Range
Over V
TTL
, V
EE
, T
C
Range
V
IN
= +2.7V
V
IN
= +5.5V
V
IN
= +0.5V
I
IN
= −18
mA
LE LOW, OE and DIR HIGH
Inputs OPEN
V
EE
= −4.2V
to
−4.8V
V
EE
= −4.2V
to
−5.7V
Note 8:
The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
3
www.fairchildsemi.com
100328
Commercial Version
(Continued)
ECL-to-TTL DC Electrical Characteristics
(Note 9)
V
EE
= −
4.2V to
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
°
C to
+
85
°
C, C
L
=
50 pF, V
TTL
= +4.5V
to
+5.5V
Symbol
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZHT
I
OZLT
I
OS
I
TTL
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
3-STATE Current Output HIGH
3-STATE Current Output LOW
Output Short-Circuit Current
V
TTL
Supply Current
−700
−150
−60
74
49
67
0.50
70
−1165
−1830
Min
2.7
2.4
Typ
3.1
2.9
0.3
0.5
−870
−1475
350
Max
Units
V
V
mV
mV
µA
µA
µA
µA
mA
mA
mA
mA
Conditions
I
OH
= −3
mA, V
TTL
=
4.75V
I
OH
= −3
mA, V
TTL
=
4.50V
I
OL
=
24 mA, V
TTL
=
4.50V
Guaranteed HIGH Signal for All Inputs
Guaranteed LOW Signal for All Inputs
V
IN
=
V
IH
(Max)
V
IN
=
V
IL
(Min)
V
OUT
= +2.7V
V
OUT
= +0.5V
V
OUT
=
0.0V, V
TTL
= +5.5V
TTL Outputs LOW
TTL Outputs HIGH
TTL Outputs in 3-STATE
DIP TTL-to-ECL AC Electrical Characteristics
(Note 9)
V
EE
= −
4.2V to
5.7V, V
TTL
= +
4.5V to
+
5.5V, V
CC
=
V
CCA
=
GND
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PHZ
t
PHZ
t
SET
t
HOLD
t
PW
(H)
t
TLH
t
THL
OE to E
n
(Cutoff to HIGH)
OE to E
n
(HIGH to Cutoff)
DIR to E
n
(HIGH to Cutoff)
T
n
to LE
T
n
to LE
Pulse Width LE
Transition Time
20% to 80%, 80% to 20%
T
N
to E
n
(Transparent)
LE to E
n
Parameter
T
C
=
0°C
Min
1.1
1.7
1.3
1.5
1.6
1.1
1.1
2.1
0.6
1.6
Max
3.5
3.6
4.2
4.5
4.3
T
C
=
25°C
Min
1.1
1.7
1.5
1.6
1.6
1.1
1.1
2.1
0.6
1.6
Max
3.6
3.7
4.4
4.5
4.3
T
C
=
85°C
Min
1.1
1.9
1.7
1.6
1.7
1.1
1.1
2.1
0.6
1.6
Max
3.8
3.9
4.8
4.6
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Units
Conditions
Note 9:
The specified limits represent the “worst” case value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
www.fairchildsemi.com
4
100328
Commercial Version
(Continued)
DIP ECL-to-TTL AC Electrical Characteristics
V
EE
= −
4.2V to
5.7V, V
TTL
= +
4.5V to
+
5.5V, V
CC
=
V
CCA
=
GND, C
L
=
50 pF
T
C
=
0°C
T
C
=
25°C
Symbol
Parameter
Min
Max
Min
Max
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
SET
t
HOLD
t
PW
(H)
OE to T
n
(Enable Time)
OE to T
n
(Disable Time)
DIR to T
n
(Disable Time)
E
n
to LE
E
n
to LE
Pulse Width LE
3.4
3.8
3.2
3.0
2.7
2.8
1.1
2.1
4.1
8.45
9.2
8.95
7.7
8.2
7.45
3.7
4.0
3.3
3.4
2.8
3.1
1.1
2.1
4.1
8.95
9.2
8.95
8.7
8.7
7.95
4.0
4.3
3.5
4.1
3.1
4.0
1.1
2.6
4.1
9.7
9.95
9.2
9.95
8.95
9.2
ns
ns
ns
ns
ns
ns
Figures 3, 5
Figures 3, 5
Figures 3, 6
Figures 3, 6
Figures 3, 4
Figures 3, 7
E
n
to T
n
(Transparent)
LE to T
n
3.1
7.2
3.1
7.2
3.3
7.7
ns
Figures 3, 4
2.3
5.6
2.4
5.6
T
C
=
85°C
Min
2.6
Max
5.9
ns
Figures 3, 4
Units
Conditions
SOIC and PLCC TTL-to-ECL AC Electrical Characteristics
V
EE
= −
4.2V to
5.7V, V
TTL
= +4.5V
to
+5.5V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PHZ
t
PHZ
t
SET
t
HOLD
t
PW
(H)
t
TLH
t
THL
t
OSHL
OE to E
n
(Cutoff to HIGH)
OE to E
n
(HIGH to Cutoff)
DIR to E
n
(HIGH to Cutoff)
T
n
to LE
T
n
to LE
Pulse Width LE
Transition Time
20% to 80%, 80% to 20%
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
t
OSLH
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
t
OST
Maximum Skew Opposite Edge
Output-to-Output Variation
Data to Output Path
t
PS
Maximum Skew
Pin (Signal) Transition Variation
Data to Output Path
Note 10:
Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same
packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in oppo-
site directions both HL and LH (t
OST
). Parameters t
OST
and t
ps
guaranteed by design.
Parameter
T
n
to E
n
(Transparent)
LE to E
n
T
C
=
0°C
Min
1.1
1.7
1.3
1.5
1.6
1.0
1.0
2.0
0.6
1.6
Max
3.3
3.4
4.0
4.3
4.1
T
C
=
25°C
Min
1.1
1.7
1.5
1.6
1.6
1.0
1.0
2.0
0.6
1.6
Max
3.4
3.5
4.2
4.3
4.1
T
C
=
85°C
Min
1.1
1.9
1.7
1.6
1.7
1.0
1.0
2.0
0.6
1.6
Max
3.6
3.7
4.6
4.4
4.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
PLCC Only
200
200
200
ps
(Note 10)
PLCC Only
200
200
200
ps
(Note 10)
PLCC Only
650
650
650
ps
(Note 10)
PLCC Only
650
650
650
ps
(Note 10)
5
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