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100393QCX

ecl-to-ttl translator

器件类别:模拟混合信号IC    驱动程序和接口   

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Fairchild
零件包装代码
LCC
包装说明
QCCJ, LDCC28,.5SQ
针数
28
Reach Compliance Code
unknown
ECCN代码
EAR99
Is Samacsys
N
最大延迟
5.3 ns
接口集成电路类型
ECL TO TTL TRANSLATOR
JESD-30 代码
S-PQCC-J28
JESD-609代码
e0
长度
11.43 mm
位数
1
功能数量
9
端子数量
28
最高工作温度
85 °C
最低工作温度
输出特性
3-STATE
输出锁存器或寄存器
LATCH
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC28,.5SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5,-4.5 V
认证状态
Not Qualified
座面最大高度
4.57 mm
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
电源电压1-最大
-5.7 V
电源电压1-分钟
-4.2 V
电源电压1-Nom
-4.5 V
表面贴装
YES
技术
ECL
温度等级
OTHER
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
11.43 mm
Base Number Matches
1
文档预览
100393 Low Power 9-Bit ECL-to-TTL Translator with Latches
February 1990
Revised November 1999
100393
Low Power 9-Bit ECL-to-TTL Translator with Latches
General Description
The 100393 is a 9-bit translator for converting F100K logic
levels to TTL logic levels. A LOW on the latch enable (LE)
latches the data at the input state. A HIGH on the LE
makes the latches transparent. A HIGH on either the ECL
or TTL output enable (OE ECL or OE TTL), holds the out-
puts in a high impedance state.
The 100393 is designed with TTL, 64 mA outputs for Bus
Driving capability. All ECL inputs have 50 kΩ pull-down
resistors. When the inputs are either unconnected or at the
same potential, the outputs will go LOW.
Features
s
64 mA I
OL
drive capability
s
2000V ESD protection
s
−4.2V
to
−5.7V
operating range
s
Latched outputs
s
TTL outputs
Ordering Code:
Order Number
100393QC
Package Number
V28A
Package Description
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
8
Q
0
–Q
8
LE
OE TTL
OE ECL
Description
Data Inputs (ECL)
Data Outputs (TTL)
Latch Enable Input (ECL)
Output Enable (TTL)
Output Enable (ECL)
© 1999 Fairchild Semiconductor Corporation
DS010650
www.fairchildsemi.com
100393
Truth Table
Inputs
OE TTL
L
L
L
H
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don’t Care
Z
=
High Impedance
Outputs
LE
H
H
L
X
X
D
N
L
H
X
X
X
Q
N
L
H
Latched
Z
Z
OE ECL
L
L
L
X
H
Logic Diagram
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2
100393
Absolute Maximum Ratings
(Note 1)
Storage Temperature (T
STG
)
Maximum Junction Temperature (T
J
)
Case Temperature under Bias (T
C
)
V
EE
Pin Potential to Ground Pin
V
TTL
Pin Potential to Ground Pin
ECL Input Voltage (DC)
TTL Input Voltage
Output Current (DC Output HIGH)
ESD (Note 2)
−65°C
to
+150°C
+150°C
0°C to
+85°C
−7.0V
to
+0.5V
−0.5V
to
+6.0V
V
EE
to
+0.5V
−0.5V
to
+7.0V
+130
mA
≥2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Supply Voltage
V
EE
V
TTL
−5.7V
to
−4.2V
+4.5V
to
+5.5V
0°C to
+85°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
ESD testing conforms to MIL-STD-883, Method 3015.
DC Electrical Characteristics
(Note 3)
V
EE
= −4.2V
to
−5.7V;
V
CC
=
V
CCA
=
GND, V
TTL
= +4.5V
to
+5.5V,
T
C
=
0
°
C to
+
85
°
C
Symbol
V
OH
V
OL
V
IH
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
ECL Inputs
OE TTL
V
IL
Input LOW Voltage
ECL Inputs
OE TTL
I
BVI
I
IH
Input Breakdown Current
ECL Input HIGH Current
ECL Inputs
OE ECL
TTL Input HIGH Current
I
IL
ECL Input LOW Current
TTL Input LOW Current
I
CEX
I
OS
I
OZH
I
OZL
V
FCD
I
EE
I
CCH
I
CCL
I
CCZ
Output HIGH Leakage Current
Output Short-Circuit Current
3-STATE Current Output HIGH
3-STATE Current Output LOW
Input Clamp Diode Voltage
V
EE
Power Supply Current
V
TTL
Power Supply Current HIGH
V
TTL
Power Supply Current LOW
V
TTL
Power Supply Current
3-STATE
−39
−100
OE TTL
ECL Inputs
OE TTL
0.5
−50
250
−225
+50
−50
−1.2
−18
29
65
49
−1165
2.0
−1830
−1475
0.8
10
240
350
5.0
Min
2.5
2.0
0.55
0.50
−870
Typ
Max
Units
V
V
mV
Guaranteed HIGH Signal for All Inputs
V
mV
Guaranteed LOW Signal for All Inputs
V
µA
µA
µA
µA
µA
µA
mA
µA
µA
V
mA
mA
mA
mA
V
OUT
=
0.0V, V
TTL
= +5.5V
V
OUT
= +2.7V
V
OUT
=
0.5V
I
IN
= −18
mA
Inputs OPEN
V
BI
=
7.0V
V
IN
=
V
IH
(Max)
V
IN
=
2.7V
V
IN
=
V
IL
(Min)
V
IN
=
0.5V
I
OH
= −1
mA
I
OH
= −15
mA
I
OL
=
64 mA
I
OL
=
24 mA
Conditions
V
IN
=
V
IL
(Min) or
V
IH
(Max)
V
IN
=
V
IL
(Min) or
V
IH
(Max)
Note 3:
The specified limits represent the “worst case” value for the parameter. Since these “worst case” values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the
tables are chosen to guarantee operation under “worst case” conditions.
3
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100393
AC Electrical Characteristics
V
EE
= −
4.2V to
5.7V, V
CC
=
GND, V
TTL
= +4.5V
to
+5.5V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
t
H
t
PW
(L)
Parameter
Propagation Delay
Data to Output
Propagation Delay
LE to Output
Output Enable Time
OE TTL
to Q
N
Output Disable Time
OE TTL
to Q
N
Output Enable Time
OE ECL
to Q
N
Output Disable Time
OE ECL
to Q
N
Setup Time, D
N
to LE
Hold Time, D
N
to LE
Pulse Width LOW, LE
T
C
=
0°C
Min
2.3
2.3
2.0
3.5
2.0
2.0
2.4
3.2
2.4
3.2
0.7
1.3
2.0
Max
4.8
5.6
5.5
8.0
6.0
5.5
5.6
8.5
6.0
7.6
T
C
= +25°C
Min
2.3
2.3
2.0
3.5
2.0
2.0
2.4
3.2
2.4
3.2
0.7
1.3
2.0
Max
4.8
5.6
5.5
8.0
6.0
5.0
5.6
8.5
6.0
7.6
T
C
= +85°C
Min
2.3
2.3
2.0
3.5
2.0
2.0
2.4
3.2
2.4
3.2
0.7
1.3
2.0
Max
5.3
6.4
5.5
8.0
6.0
5.0
5.6
8.5
6.0
7.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Figures 1, 2
Figures 1, 2
Figure 3
Figure 3
Figure 4
Figure 4
Figures 1, 2
Figures 1, 2
Figures 1Figure 2
Test Circuit
Switch Positions
for Parameter Testing
Parameter
t
PLH
, t
PHL
t
PHZ
, t
PZH
t
PLZ
, t
PZL
S-Position
Open
Open
Open
FIGURE 1. AC Test Setup
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4
100393
Switching Waveforms
FIGURE 2. Propagation Delays, Setup and Hold Times, and Pulse Width
FIGURE 3. Enable and Disable Waveforms, OE TTL
FIGURE 4. Enable and Disable Waveforms, OE ECL
5
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