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10AS066K3F35I2LG

IC SOC FPGA 396 I/O 1152FBGA

器件类别:可编程逻辑器件    可编程逻辑   

厂商名称:Intel(英特尔)

厂商官网:http://www.intel.com/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Intel(英特尔)
包装说明
35 X 35 MM, ROHS COMPLIANT, FBGA-1152
Reach Compliance Code
compliant
JESD-30 代码
S-PBGA-B1152
长度
35 mm
输入次数
396
逻辑单元数量
660000
输出次数
396
端子数量
1152
最高工作温度
100 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
BGA
封装等效代码
BGA1152,34X34,40
封装形状
SQUARE
封装形式
GRID ARRAY
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
0.9 V
可编程逻辑类型
FIELD PROGRAMMABLE GATE ARRAY
认证状态
Not Qualified
座面最大高度
3.5 mm
最大供电电压
0.93 V
最小供电电压
0.87 V
标称供电电压
0.9 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子形式
BALL
端子节距
1 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
35 mm
文档预览
Intel
®
Arria
®
10 Device Datasheet
Subscribe
Send Feedback
A10-DATASHEET | 2018.06.15
Latest document on the web:
PDF
|
HTML
Contents
Contents
Intel
®
Arria
®
10 Device Datasheet............................................................................................................................................. 3
Electrical Characteristics...................................................................................................................................................... 3
Operating Conditions.................................................................................................................................................. 4
Switching Characteristics....................................................................................................................................................24
Transceiver Performance Specifications....................................................................................................................... 25
Core Performance Specifications.................................................................................................................................36
Periphery Performance Specifications.......................................................................................................................... 46
HPS Specifications....................................................................................................................................................55
Configuration Specifications................................................................................................................................................ 83
POR Specifications....................................................................................................................................................83
JTAG Configuration Timing.........................................................................................................................................84
FPP Configuration Timing.......................................................................................................................................... 85
AS Configuration Timing............................................................................................................................................89
DCLK Frequency Specification in the AS Configuration Scheme....................................................................................... 90
PS Configuration Timing............................................................................................................................................90
Initialization............................................................................................................................................................ 92
Configuration Files....................................................................................................................................................92
Minimum Configuration Time Estimation......................................................................................................................94
Remote System Upgrades......................................................................................................................................... 96
User Watchdog Internal Circuitry Timing Specifications..................................................................................................96
I/O Timing....................................................................................................................................................................... 96
Programmable IOE Delay................................................................................................................................................... 97
Glossary.......................................................................................................................................................................... 98
Document Revision History for the Intel Arria 10 Device Datasheet.........................................................................................101
Intel
®
Arria
®
10 Device Datasheet
2
A10-DATASHEET | 2018.06.15
Intel
®
Arria
®
10 Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing
for Intel
®
Arria
®
10 devices.
Intel Arria 10 devices are offered in extended, industrial, and automotive grades. Extended devices are offered in –E1
(fastest), –E2, and –E3 speed grades. Industrial grade devices are offered in the –I1, –I2, and –I3 speed grades. Automotive
devices are offered in the –A3 speed grade and transceiver speed grade 4.
Note:
The specifications for the automotive devices are preliminary, pending characterization.
The suffix after the speed grade denotes the power options offered in Intel Arria 10 devices.
L—Low static power
S—Standard power
V—Supported with the SmartVID feature (lowest static power)
H—High performance power
Related Information
Intel Arria 10 Device Overview
Provides more information about the densities and packages of devices in the Intel Arria 10 family.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel Arria 10 devices.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no
responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by
Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Intel
®
Arria
®
10 Device Datasheet
A10-DATASHEET | 2018.06.15
Operating Conditions
Intel Arria 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Intel Arria 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel Arria 10 devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
Caution:
Table 1.
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Absolute Maximum Ratings for Intel Arria 10 Devices
Symbol
V
CC
V
CCP
V
CCERAM
V
CCPT
V
CCBAT
V
CCPGM
V
CCIO
Core voltage power supply
Periphery circuitry and transceiver fabric interface power supply
Embedded memory power supply
Power supply for programmable power technology and I/O pre-driver
Battery back-up power supply for design security volatile key register
Configuration pins power supply
I/O buffers power supply
Description
Condition
(1)
Minimum
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
Maximum
1.21
1.21
1.36
2.46
2.46
2.46
4.10
2.46
2.46
1.34
1.34
2.46
Unit
V
V
V
V
V
V
V
V
V
V
V
V
continued...
3 V I/O
LVDS I/O
V
CCA_PLL
V
CCT_GXB
V
CCR_GXB
V
CCH_GXB
Phase-locked loop (PLL) analog power supply
Transmitter power supply
Receiver power supply
Transceiver output buffer power supply
(1)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
Intel
®
Arria
®
10 Device Datasheet
4
Intel
®
Arria
®
10 Device Datasheet
A10-DATASHEET | 2018.06.15
Symbol
V
CCL_HPS
V
CCIO_HPS
Description
HPS core voltage and periphery circuitry power supply
HPS I/O buffers power supply
Condition
3 V I/O
LVDS I/O
Minimum
–0.50
–0.50
–0.50
–0.50
–0.50
–25
(2)(3)(4)(5)
(6)
Maximum
1.27
4.10
2.46
2.46
2.46
25
125
150
Unit
V
V
V
V
V
mA
°C
°C
V
CCIOREF_HPS
V
CCPLL_HPS
I
OUT
T
J
T
STG
HPS I/O pre-driver power supply
HPS PLL power supply
DC output current per pin
Operating junction temperature
Storage temperature (no bias)
–55
–65
Related Information
AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices
Provides the power sequencing requirements for Intel Arria 10 devices.
Power-Up and Power-Down Sequences, Power Management in Intel Arria 10 Devices chapter
Provides the power sequencing requirements for Intel Arria 10 devices.
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
(2)
The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down
conditions is 10 mA.
Total current per LVDS I/O bank must not exceed 100 mA.
Voltage level must not exceed 1.89 V.
Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.
Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power
sequencing requirement. For more details, refer to
AN 692: Power Sequencing Considerations for Intel Cyclone
®
10 GX, Intel Arria 10,
and Intel Stratix
®
10 Devices
and
Power Management in Intel Arria 10 Devices chapter.
(3)
(4)
(5)
(6)
Intel
®
Arria
®
10 Device Datasheet
5
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