Intel
®
MAX
®
10 Clocking and PLL
User Guide
Updated for Intel
®
Quartus
®
Prime Design Suite:
18.0
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UG-M10CLKPLL | 2018.06.15
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Contents
Contents
1. Intel
®
MAX
®
10 Clocking and PLL Overview................................................................... 4
1.1. Clock Networks Overview........................................................................................4
1.2. Internal Oscillator Overview.................................................................................... 4
1.3. PLLs Overview.......................................................................................................4
2. Intel MAX 10 Clocking and PLL Architecture and Features.............................................. 6
2.1. Clock Networks Architecture and Features................................................................6
2.1.1. Global Clock Networks................................................................................6
2.1.2. Clock Pins Introduction............................................................................... 6
2.1.3. Clock Resources........................................................................................ 7
2.1.4. Global Clock Network Sources..................................................................... 7
2.1.5. Global Clock Control Block.......................................................................... 9
2.1.6. Global Clock Network Power Down............................................................. 11
2.1.7. Clock Enable Signals................................................................................ 12
2.2. Internal Oscillator Architecture and Features........................................................... 13
2.3. PLLs Architecture and Features............................................................................. 13
2.3.1. PLL Architecture.......................................................................................13
2.3.2. PLL Features........................................................................................... 15
2.3.3. PLL Locations.......................................................................................... 15
2.3.4. Clock Pin to PLL Connections..................................................................... 17
2.3.5. PLL Counter to GCLK Connections.............................................................. 17
2.3.6. PLL Control Signals.................................................................................. 18
2.3.7. Clock Feedback Modes.............................................................................. 19
2.3.8. PLL External Clock Output......................................................................... 23
2.3.9. ADC Clock Input from PLL......................................................................... 24
2.3.10. Spread-Spectrum Clocking...................................................................... 24
2.3.11. PLL Programmable Parameters................................................................. 24
2.3.12. Clock Switchover....................................................................................27
2.3.13. PLL Cascading........................................................................................31
2.3.14. PLL Reconfiguration................................................................................ 32
3. Intel MAX 10 Clocking and PLL Design Considerations.................................................. 34
3.1. Clock Networks Design Considerations.................................................................... 34
3.1.1. Guideline: Clock Enable Signals................................................................. 34
3.1.2. Guideline: Connectivity Restrictions............................................................ 34
3.2. Internal Oscillator Design Considerations................................................................ 34
3.2.1. Guideline: Connectivity Restrictions............................................................ 34
3.3. PLLs Design Considerations................................................................................... 35
3.3.1. Guideline: PLL Control Signals................................................................... 35
3.3.2. Guideline: Connectivity Restrictions............................................................ 35
3.3.3. Guideline: Self-Reset................................................................................ 35
3.3.4. Guideline: Output Clocks...........................................................................36
3.3.5. Guideline: PLL Cascading.......................................................................... 36
3.3.6. Guideline: Clock Switchover...................................................................... 37
3.3.7. Guideline: .mif Streaming in PLL Reconfiguration..........................................38
3.3.8. Guideline: scandone Signal for PLL Reconfiguration...................................... 38
Intel
®
MAX
®
10 Clocking and PLL User Guide
2
Contents
4. Intel MAX 10 Clocking and PLL Implementation Guides................................................ 39
4.1. ALTCLKCTRL Intel FPGA IP Core............................................................................. 39
4.2. ALTPLL Intel FPGA IP Core.....................................................................................39
4.2.1. Expanding the PLL Lock Range...................................................................40
4.2.2. Programmable Bandwidth with Advanced Parameters....................................41
4.2.3. PLL Dynamic Reconfiguration Implementation.............................................. 42
4.2.4. Dynamic Phase Configuration Implementation............................................. 46
4.3. ALTPLL_RECONFIG Intel FPGA IP Core.................................................................... 49
4.3.1. Obtaining the Resource Utilization Report................................................... 49
4.4. Internal Oscillator Intel FPGA IP Core..................................................................... 50
5. ALTCLKCTRL Intel FPGA IP Core References................................................................ 51
5.1. ALTCLKCTRL IP Core Parameters............................................................................ 51
5.2. ALTCLKCTRL IP Core Ports and Signals....................................................................52
6. ALTPLL Intel FPGA IP Core References......................................................................... 53
6.1. ALTPLL IP Core Parameters....................................................................................53
6.1.1. Operation Modes Parameter Settings.......................................................... 53
6.1.2. PLL Control Signals Parameter Settings....................................................... 53
6.1.3. Programmable Bandwidth Parameter Settings.............................................. 54
6.1.4. Clock Switchover Parameter Settings.......................................................... 54
6.1.5. PLL Dynamic Reconfiguration Parameter Settings......................................... 55
6.1.6. Dynamic Phase Configuration Parameter Settings......................................... 55
6.1.7. Output Clocks Parameter Settings.............................................................. 56
6.2. ALTPLL IP Core Ports and Signals........................................................................... 57
7. ALTPLL_RECONFIG Intel FPGA IP Core References...................................................... 60
7.1. ALTPLL_RECONFIG IP Core Parameters................................................................... 60
7.2. ALTPLL_RECONFIG IP Core Ports and Signals........................................................... 61
7.3. ALTPLL_RECONFIG IP Core Counter Settings............................................................63
8. Internal Oscillator Intel FPGA IP Core References........................................................ 66
8.1. Internal Oscillator IP Core Parameters.................................................................... 66
8.2. Internal Oscillator IP Core Ports and Signals............................................................ 66
9. Intel MAX 10 Clocking and PLL User Guide Archives..................................................... 67
10. Document Revision History for the Intel MAX 10 Clocking and PLL User Guide........... 68
Intel
®
MAX
®
10 Clocking and PLL User Guide
3
UG-M10CLKPLL | 2018.06.15
1. Intel
®
MAX
®
10 Clocking and PLL Overview
1.1. Clock Networks Overview
Intel
®
MAX
®
10 devices support global clock (GCLK) networks.
Clock networks provide clock sources for the core. You can use clock networks in high
fan-out global signal network such as reset and clear.
1.2. Internal Oscillator Overview
Internal oscillators enable implementing designs that require clocking, thereby saving
on-board space and costs associated with external clocking circuitry.
Intel MAX 10 devices offer built-in internal oscillator up to 116 MHz.
You can enable or disable the internal oscillator.
Related Information
AN 496: Using the Internal Oscillator IP Core
Provides more information about the internal oscillator.
1.3. PLLs Overview
Phase-locked loops (PLLs) provide robust clock management and synthesis for device
clock management, external system clock management, and I/O interface clocking.
You can use the PLLs as follows:
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Zero-delay buffer
Jitter attenuator
Low-skew fan-out buffer
Frequency synthesizer
Reduce the number of oscillators required on the board
Reduce the clock pins used in the device by synthesizing multiple clock
frequencies from a single reference clock source
On-chip clock de-skew
Dynamic phase shift
Counters reconfiguration
Bandwidth reconfiguration
Programmable output duty cycle
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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1. Intel
®
MAX
®
10 Clocking and PLL Overview
UG-M10CLKPLL | 2018.06.15
•
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PLL cascading
Reference clock switchover
Drive the analog-to-digital converter (ADC) clock
Intel
®
MAX
®
10 Clocking and PLL User Guide
5
电源技术
