DATASHEET
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
General Description
The IDT1337G device is a low power serial real-time clock
(RTC) device with two programmable time-of-day alarms
and a programmable square-wave output. Address and
data are transferred serially through an I
2
C bus. The device
provides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is
automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator.
IDT1337G
Features
•
Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
•
Packaged in 8-pin MSOP, 8-pin SOIC, 16-pin VFQFPN
(without integrated crystal), or 16-pin SOIC
(surface-mount package with an integrated crystal)
Applications
•
•
•
•
•
•
Telecommunication (Routers, Switches, Servers)
Handhelds (GPS, POS terminals, MP3 players)
Set-Top Box, Digital Recording,
Office (Fax/Printers, Copiers)
Medical (Glucometer, Medicine Dispensers)
Other (Thermostats, Vending Machines, Modems, Utility
Meters, Digital Photo Frame devices)
•
•
•
•
I
2
C Serial interface (Normal and Fast modes)
Two time-of-day alarms
Oscillator Stop Flag
Programmable square-wave output defaults to 32 kHz on
power-up
•
Operating voltage of 1.8 to 5.5 V
•
Industrial temperature range (-40 to +85°C)
Block Diagram
VCC
Crystal inside package
for 16-pin SOIC ONLY
X1
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
32.768 kHz
Oscillator and
Divider
MUX/
Buffer
SQW/INTB
INTA
X2
Control
Logic
Clock,
Calendar
Counter
SCL
SDA
I
2
C
Interface
1 Byte
Control
7 Bytes
Buffer
Alarm
Registers
GND
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
1
IDT1337G
REV M 073013
IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
RTC
Pin Assignment
(8-pin MSOP/SOIC)
X1
X2
INTA
GND
1
2
3
4
8
VCC
SQW/INTB
SCL
SDA
Pin Assignment
(16-pin VFQFPN)
NC
NC
13
IDT1337G
7
6
5
NC
INTA
GND
NC
X2
X1
1
NC
VCC
SQW/INTB
Pin Assignment
(16-pin SOIC)
SCL
SQW/INTB
VCC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
16
15
14
SDA
GND
INTA
NC
NC
NC
NC
NC
5
9
NC
NC
IDT1337G
13
12
11
10
9
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
2
SDA
SCL
NC
IDT1337G
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IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
RTC
Pin Descriptions
Pin Number
MSOP SOIC
1
2
—
—
QFN
14
15
Pin
Name
X1
X2
Pin Description/Function
Connections for standard 32.768 kHz quartz crystal. The internal oscillator
circuitry is designed for operation with a crystal having a specified load
capacitance (CL) of 7 pF. An external 32.768 kHz oscillator can also drive the
IDT1337G. In this configuration, the X1 pin is connected to the external
oscillator signal and the X2 pin is left floating.
Interrupt output. When enabled, INTA is asserted low when the time/day/date
matches the values set in the alarm registers. This pin is an open-drain output
and requires an external pull-up resistor (10 k typical).
Connect to ground. DC power is provided to the device on these pins.
Serial data input/output. SDA is the input/output pin for the I
2
C serial interface.
The SDA pin is an open-drain output and requires an external pull-up resistor
(2 k typical).
Serial clock input. SCL is used to synchronize data movement on the serial
interface. The SCL pin is an open-drain output and requires an external pull-up
resistor (2 k typical).
3
4
5
14
15
16
2
3
6
INTA
GND
SDA
6
1
7
SCL
7
2
10
Square-Wave/Interrupt output. Programmable square-wave or interrupt output
signal. The SQW/INT pin is an open-drain output and requires an external
SQW/INTB
pull-up resistor (10 k typical). This pin can also function as an additional
interrupt pin under certain conditions (see page 6 for details).
VCC
NC
Primary power supply. DC power is applied to this pin.
No connect. These pins are unused and must be connected to ground.
8
—
3
4 - 13
11
1,4,5,8,9,
12,13,16
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
3
IDT1337G
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IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
RTC
Typical Operating Circuit
V
CC
V
CC
CRYSTAL
V
CC
2k
CPU
2k
X1
SCL
SDA
X2
V
CC
SQW/INTB
10k
10k
IDT1337G
GND
INTA
Detailed Description
Communications to and from the IDT1337G occur serially
over an I
2
C bus. The IDT1337G operates as a slave device
on the serial bus. Access is obtained by implementing a
START condition and providing a device identification code,
followed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The device
is fully accessible through the I
2
C interface whenever VCC
is between 5.5 V and 1.8 V. I
2
C operation is not guaranteed
when VCC is below 1.8 V. The IDT1337G maintains the time
and date when VCC is as low as 1.3 V.
The following sections discuss in detail the Oscillator block,
Clock/Calendar Register Block and Serial I
2
C block.
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1337G RTC are:
•
Recommended Load Capacitance
•
Crystal Effective Series Resistance (ESR)
•
Frequency Tolerance
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
4
IDT1337G
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IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
RTC
Note:
IDT1337CSRI integrates a standard 32.768 kHz
crystal in the package and contributes an additional
frequency error of 10ppm at nominal
V
CC
(+3.3 V) and
T
A
=
+25°C.
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
PCB Layout
Frequency Tolerance
The frequency tolerance for 32 kHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1337G
typically have a frequency tolerance of +/-20ppm at +25°C.
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
Parameter
Nominal Freq.
Series Resistance
Load Capacitance
1337G
Symbol
f
O
ESR
C
L
Min
Typ
32.768
Max Units
kHz
80
k
pF
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32 KHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
7
PCB Design Consideration
•
Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
•
Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
•
Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
•
The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
•
To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE
5
IDT1337G
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