Preliminary Data Sheet
July 1999
FlashDSP
®
1609F
Digital Signal Processor
1 Features
s
2 Description
The
FlashDSP
1609F is a 16-bit, fixed-point digital sig-
nal processor (DSP) based on the DSP1600 core. It is
programmable to perform a wide variety of fixed-point
signal processing functions. A member of the
DSP1600 family, the
FlashDSP
1609F includes a mix of
peripherals specifically intended to support process-
ing-intensive but cost-sensitive applications. In addition
to the core, the
FlashDSP
1609F consists of the follow-
ing peripheral blocks: a programmable phase-locked
loop (PLL), synchronous serial interface unit (SSI), four
I/O ports (IOPs), two timer units, a watchdog timer, one
dual-channel serial I/O interface (SIO), and a JTAG
interface; as well as 4 Kwords of RAM. The
FlashDSP
1609F is part of a low-cost, high-perfor-
mance solution for consumer product applications.
The
FlashDSP1609F
is available in the following pack-
ages:
s
s
s
12.5 ns instruction cycle time (80 MIPS) at 3.3 V
operation
Power-saving features:
— Low-power 0.35
µm
CMOS technology; fully
static design
— Active power: 6.5 mW/MIPS at 3.3 V
— Low-power stopclk: 66 µW at 3.3 V
For DSP1609F: 32 Kwords internal flash ROM
4 Kwords internal RAM
16 x 16-bit multiplication and 36-bit accumulation
in one instruction cycle
Two 36-bit accumulators
Instruction cache for high-speed, program-efficient,
zero-overhead looping
One external vectored interrupt
Two 64 Kword address spaces
Programmable phase-locked loop
Three 8-bit and one 4-bit I/O ports for flexible sta-
tus or control pins
Two interrupt timers and one watchdog timer
44-pin PLCC and 44-pin MQFP packages
High- and low-frequency clock options
Synchronous serial interface unit
Object code upward compatible with DSP1600
Digital Signal Processor family
Supported by DSP1609 support tools
Full-speed in-circuit emulation HDS (HD-sup-
ported)
One dual-channel serial I/O port
One bit manipulation unit
DRAM control interface
s
s
s
s
s
s
s
s
s
44-pin PLCC (See Figure 1 on page 8.)
44-pin MQFP (See Figure 2 on page 9.)
s
s
s
s
s
The
FlashDSP1609F
achieves high throughput without
programming restrictions or latencies due to its parallel
pipelined architecture. The processor has an arith-
metic unit capable of a 16 x 16-bit multiplication and
36-bit accumulation, or a 32-bit ALU operation in one
instruction cycle. Data is accessed from memory
through two independent addressing units.
A fully static, low-power, 0.35
µm
CMOS design and a
low-power standby mode support power-sensitive
equipment applications. A single external crystal
allows the use of a high-frequency and a low-
frequency clock. Under program control, the
FlashDSP
1609F can be switched between the high-
frequency and low-frequency clock options. When
switched to the low-frequency clock, the power is
reduced and can be further reduced using a stop-clock
mode.
The
FlashDSP1609F
device is the development plat-
form for the DSP1609. To support full-speed in-circuit
emulation, the
FlashDSP
1609F device includes an
internal HDS module and an internal flash ROM for
program development.
s
s
s
s
s
FlashDSP1609F
Digital Signal Processor
Preliminary Data Sheet
July 1999
Table of Contents
Contents
1
2
3
4
Page
Features ..............................................................................................................................................................1
Description .........................................................................................................................................................1
Pin Information ................................................................................................................................................... 8
Hardware Architecture ..................................................................................................................................... 16
4.1
FlashDSP
1609F Architectural Overview ................................................................................................ 16
4.1.1 DSP1600 Core ...........................................................................................................................19
4.1.2 Dual-Port RAM (DPRAM) ..........................................................................................................19
4.1.3 Flash Read-Only Memory (ROM).............................................................................................. 19
4.1.4 Timers ....................................................................................................................................... 19
4.1.5 Watchdog Timer ........................................................................................................................19
4.1.6 Input/Output Ports (IOP)............................................................................................................ 19
4.1.7 JTAG ......................................................................................................................................... 19
4.1.8 Synchronous Serial Interface Units (SSI) ..................................................................................20
4.1.9 Clock Generation....................................................................................................................... 20
4.1.10 Dual-Channel Serial I/O Port (SIO) ...........................................................................................20
4.1.11 Bit Manipulation Unit (BMU) ......................................................................................................20
4.1.12 DRAM Control Interface (DRC) .................................................................................................20
4.2 DSP1600 Core Architectural Overview .................................................................................................. 21
4.2.1 System Cache and Control Section (SYS) ................................................................................23
4.2.2 Data Arithmetic Unit (DAU) .......................................................................................................23
4.2.3 Y Space Address Arithmetic Unit (YAAU) .................................................................................23
4.2.4 X Space Address Arithmetic Unit (XAAU) .................................................................................23
4.3 Interrupts, Trap, and Low-Power Standby Mode ....................................................................................24
4.3.1 Interruptibility .............................................................................................................................24
4.3.2 Vectored Interrupts ....................................................................................................................24
4.3.3 External Interrupt Pin (INTB) .....................................................................................................24
4.3.4 IOPA Interrupt ...........................................................................................................................25
4.3.5 Clearing Interrupts .....................................................................................................................25
4.3.6 Power-Saving Modes ................................................................................................................ 25
4.4 Memory Maps and Wait-States .............................................................................................................. 25
4.4.1 Instruction/Coefficient Memory Map Selection ..........................................................................25
4.4.2 Data Memory Map Selection .....................................................................................................26
4.5 Clock Generation.................................................................................................................................... 27
4.5.1 Functional Overview.................................................................................................................. 27
4.5.2 Core Clock Switching ................................................................................................................ 29
4.6 DRAM Control Interface .........................................................................................................................30
4.6.1 DRC Refresh Timing ..................................................................................................................30
4.6.2 DRC Refresh Programming Procedure..................................................................................... 31
4.7 Synchronous Serial Interface (SSI) ........................................................................................................32
4.7.1 SSI Operation ............................................................................................................................33
4.8 I/O Ports (IOP)........................................................................................................................................ 34
4.8.1 IOP Operation ...........................................................................................................................34
4.8.2 IOPA Interrupt Circuitry ............................................................................................................. 34
4.8.3 Pin Multiplexing Control............................................................................................................. 35
4.9 Timers .................................................................................................................................................... 36
4.10 Watchdog Timer .....................................................................................................................................36
4.11 Dual-Channel Serial I/O Port (SIO) for
FlashDSP
1609F ........................................................................37
4.11.1
FlashDSP1609F
SIO Architecture............................................................................................. 38
4.11.2
FlashDSP1609F
SIO Operation ................................................................................................39
4.11.3
FlashDSP
1609F SIO Programming Examples ......................................................................... 42
4.12 Bit Manipulation Unit (BMU) ...................................................................................................................43
Lucent Technologies Inc.
2
Preliminary Data Sheet
July 1999
FlashDSP1609F
Digital Signal Processor
Table of Contents
(continued)
Contents
5
Page
Software Architecture....................................................................................................................................... 44
5.1 Instruction Set ........................................................................................................................................44
5.1.1 F1 Multiply/ALU Instructions ......................................................................................................44
5.1.2 F2 Special Function Instructions ...............................................................................................46
5.1.3 Control Instructions ...................................................................................................................47
5.1.4 Conditional Mnemonics (Flags) .................................................................................................48
5.1.5 F3 ALU Instructions................................................................................................................... 49
5.1.6 F4 BMU Instructions ..................................................................................................................49
5.1.7 Cache Instructions..................................................................................................................... 51
5.1.8 Data Move Instructions ..............................................................................................................52
5.2 Register Settings .................................................................................................................................... 53
5.3 Reset States ...........................................................................................................................................66
5.4 Instruction Set Formats ..........................................................................................................................67
5.4.1 Multiply/ALU Instructions ...........................................................................................................67
5.4.2 Special Function Instructions .................................................................................................... 67
5.4.3 Control Instructions ................................................................................................................... 68
5.4.4 Data Move Instructions.............................................................................................................. 69
5.4.5 Cache Instructions..................................................................................................................... 69
5.4.6 Field Descriptions ...................................................................................................................... 70
6 Device Requirements and Characteristics .......................................................................................................74
6.1 Absolute Maximum Ratings ....................................................................................................................74
6.2 Handling Precautions .............................................................................................................................74
6.3 Recommended Operating Conditions ....................................................................................................75
6.4 Decoupling Requirements ...................................................................................................................... 75
6.5 Package Thermal Considerations ..........................................................................................................75
7 Electrical Requirements and Characteristics ...................................................................................................76
7.1 Typical Power Dissipation ......................................................................................................................78
7.2 Input and I/O Buffer Power Dissipation ..................................................................................................80
8 Timing Requirements and Characteristics .......................................................................................................81
8.1 Input Clock Options ................................................................................................................................81
8.2 DSP Clock Generation ........................................................................................................................... 82
8.3 Reset Synchronization ........................................................................................................................... 83
8.4 JTAG I/O Specifications .........................................................................................................................84
8.5 Interrupt ..................................................................................................................................................85
8.6 Input/Output Ports (IOP)......................................................................................................................... 86
8.7 Synchronous Serial Interface (SSI) Specifications .................................................................................87
8.8 Serial I/O Specifications .........................................................................................................................90
9 Crystal Oscillator Electrical Requirements and Characteristics .......................................................................95
9.1 Crystal Oscillator ....................................................................................................................................95
9.1.1 Crystal Oscillator Power Dissipation ......................................................................................... 95
9.1.2 Crystal Oscillator External Components ....................................................................................95
9.1.3 Crystal Oscillator Negative Resistance Curves .........................................................................96
9.2 Frequency Accuracy Considerations ......................................................................................................97
10 Outline Diagrams ...........................................................................................................................................100
10.1 44-Pin PLCC ........................................................................................................................................ 100
10.2 44-Pin MQFP........................................................................................................................................ 101
11 Ordering Information ...................................................................................................................................... 102
11.1 Device Coding ...................................................................................................................................... 102
11.2 Mask-Programmable Options............................................................................................................... 102
12 Product Preview: DSP1609 ............................................................................................................................103
12.1 DSP1609 Features ...............................................................................................................................103
12.2 DSP1609 Description ...........................................................................................................................103
Lucent Technologies Inc.
3
FlashDSP1609F
Digital Signal Processor
Preliminary Data Sheet
July 1999
Table of Contents
(continued)
Figure
Page
Figure 1.
FlashDSP
1609F 44-Pin PLCC Pin Diagram ............................................................................................. 8
Figure 2.
FlashDSP
1609F 44-Pin MQFP Pin Diagram ............................................................................................ 9
Figure 3.
FlashDSP
1609F Pinout by Group ........................................................................................................... 10
Figure 4.
FlashDSP
1609F Block Diagram.............................................................................................................. 17
Figure 5. DSP1600 Core Block Diagram................................................................................................................ 21
Figure 6. Clock Generation Overview..................................................................................................................... 28
Figure 7. DRC Refresh Timing ............................................................................................................................... 30
Figure 8. DRC Refresh Period................................................................................................................................ 31
Figure 9. SSI Interconnections ............................................................................................................................... 32
Figure 10.
FlashDSP1609F
SIO Block Diagram .................................................................................................... 38
Figure 11. 16-Bit Serial Transfer in Active, Single-Channel Mode ......................................................................... 39
Figure 12. 64-Bit and 80-Bit Serial Transfers in Active, Single-Channel Mode ...................................................... 40
Figure 13. Serial Transfer in Passive, Dual-Channel Mode ................................................................................... 41
Figure 14. Serial Transfer in Active, Dual-Channel Mode with Delayed Load........................................................ 41
Figure 15. Plot of V
OH
vs. I
OH
Under Typical Operating Conditions........................................................................ 77
Figure 16. Plot of V
OL
vs. I
OL
Under Typical Operating Conditions ......................................................................... 77
Figure 17. I/O Clock Timing Diagram ..................................................................................................................... 82
Figure 18. Reset Synchronization Timing............................................................................................................... 83
Figure 19. JTAG Timing Diagram........................................................................................................................... 84
Figure 20. Interrupt Timing Diagram....................................................................................................................... 85
Figure 21. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) .................................................. 86
Figure 22. SSI Transfer Timing (SPHA = 0) ........................................................................................................... 87
Figure 23. SSI Transfer Timing (SPHA = 1) ........................................................................................................... 88
Figure 24. SIO Active Output Timing Diagram ....................................................................................................... 90
Figure 25. SIO Passive Output Timing Diagram .................................................................................................... 91
Figure 26. SIO Active Input Timing Diagram .......................................................................................................... 92
Figure 27. SIO Passive Input Timing Diagram ....................................................................................................... 93
Figure 28. Serial I/O Active Clocks Timing Diagram .............................................................................................. 94
Figure 29. Fundamental Crystal Configuration....................................................................................................... 95
Figure 30. 3.3 V Crystal Oscillator Negative Resistance Curves ........................................................................... 96
Figure 31. Components of Load Capacitance for Crystal Oscillator....................................................................... 97
4
Lucent Technologies Inc.
Preliminary Data Sheet
July 1999
FlashDSP1609F
Digital Signal Processor
Table of Contents
(continued)
Table
Page
Table 1.
FlashDSP1609F
Pinout ............................................................................................................................ 11
Table 2.
FlashDSP1609F
Power Supply and Ground Pins ....................................................................................12
Table 3. System Interface .......................................................................................................................................13
Table 4. Synchronous Serial Interface (SSI) ..........................................................................................................13
Table 5. I/O Port Interface (IOP) .............................................................................................................................14
Table 6. JTAG Test Mode Interface .......................................................................................................................15
Table 7. DRAM Control Interface ...........................................................................................................................15
Table 8. PWR/GND ................................................................................................................................................15
Table 9.
FlashDSP
1609F Block Diagram Legend ..................................................................................................18
Table 10. DOUT Pin Output Functions ...................................................................................................................20
Table 11. DSP1600 Core Block Diagram Legend ..................................................................................................22
Table 12. Interrupt Vectors .....................................................................................................................................24
Table 13. Instruction/Coefficient Memory Map (X Memory Space) ........................................................................26
Table 14. Data (Y) Memory Map ............................................................................................................................26
Table 15. Clock Options .........................................................................................................................................27
Table 16. Clock Switch Latencies ...........................................................................................................................29
Table 17. Core Clock Stabilization Requirements ..................................................................................................29
Table 18. DRC Refresh Timing ..............................................................................................................................30
Table 19. SSI Pin Descriptions ...............................................................................................................................33
Table 20. IOP Operation .........................................................................................................................................34
Table 21. IOP Pin Multiplexing ...............................................................................................................................35
Table 22. SIO Read/Write Pointer Operation .........................................................................................................40
Table 23. Instruction Set Operators ........................................................................................................................44
Table 24. F1 Multiply/ALU Instructions ...................................................................................................................45
Table 25. Replacement Table for F1 Multiply/ALU Instructions .............................................................................45
Table 26. F2 Special Function Instructions ............................................................................................................46
Table 27. Replacement Table for F2 Special Function Instructions .......................................................................46
Table 28. Control Instructions .................................................................................................................................47
Table 29. Replacement Table for Control Instructions ...........................................................................................47
Table 30.
FlashDSP1609F
Conditional Mnemonics ...............................................................................................48
Table 31. F3 ALU Instructions ................................................................................................................................49
Table 32. Replacement Table for F3 ALU Instructions ...........................................................................................49
Table 33. Replacement Table for F4 BMU Instructions ..........................................................................................50
Table 34. Cache Instructions ..................................................................................................................................51
Table 35. Replacement Table for Cache Instructions ............................................................................................51
Table 36. Data Move Instructions ...........................................................................................................................52
Table 37. Replacement Table for Data Move Instructions .....................................................................................52
Table 38.
alf
(Standby and Memory Map) Register ...............................................................................................53
Table 39.
auc
(Arithmetic Unit Control) Register ....................................................................................................54
Table 40.
cbit<a—d>
(IOP Control Bit) and
sbit<a—d>
(IOP Status Bit) Registers .............................................54
Table 41.
chipc
Register Fields .............................................................................................................................55
Table 42.
chipo
Register Fields .............................................................................................................................56
Table 43.
clkc
Register Fields ................................................................................................................................57
Table 44.
drc
Register Fields .................................................................................................................................58
Table 45.
inc
(Interrupt Control) Register ...............................................................................................................58
Table 46.
ins
(Interrupt Status) Register ................................................................................................................58
Table 47. IOPUC<a—d> Register Fields ...............................................................................................................59
Table 48. JTAG ID Register (32-bit) .......................................................................................................................60
Table 49. JTAG ROMCODE Letter Values ............................................................................................................60
Table 50.
pllc
Register Fields ................................................................................................................................61
Lucent Technologies Inc.
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