Multilayer
Summary
Ceramic
Capacitors
Technical
Definitions of Ultra-Stable and Stable
Multilayer Ceramic Capacitors are generally divided into classes
which are defined by the capacitance temperature characteristics
over specified temperature ranges.
These are designated by alpha numeric codes.
Code definitions are summarised below and are also available in the
relevant national and international specifications.
1. C0G - Ultra Stable Class 1 Ceramic (EIA Class 1)
Spec.
CECC
EIA
MIL
Classification
1B/CG
C0G (NP0)
CG (BP)
Temperature
range °C
-55 +125
-55 +125
-55 +125
Maximum
capacitance change
0 ± 30ppm/°C
0 ± 30ppm/°C
0 ± 30ppm/°C
Syfer
dielectric code
C
C
C
Capacitors within this class have a dielectric constant range from 10
to 100. They are used in applications which require ultra stable
dielectric characteristics with negligible dependence of capacitance
and dissipation factor with time, voltage and frequency. They
exhibit the following characteristics:-
a) Time does not significantly affect capacitance and dissipation
factor (Tan
δ)
– no ageing.
b) Capacitance and dissipation factor are not affected by voltage.
c) Linear temperature coefficient.
2. X7R – Stable Class II Ceramic (EIA Class II)
Maximum capacitance change %
over temperature range
No DC volt applied
±20
±15
±15
±15
±15
±20
Rated DC Volt
+20 -30
+15 -25
-
+15 -25
+20 -30
Syfer
dielectric
code
R
X
B
X
B
R
Spec.
CECC
Classification
2C1
2R1
2X1
X7R
BX
BZ
Temperature
range °C
-55 +125
-55 +125
-55 +125
-55 +125
-55 +125
-55 +125
EIA
MIL
Capacitors of this type have a dielectric constant range of 1000-
4000, and also have a non-linear temperature characteristic which
exhibits a dielectric constant variation of less than ±15% (2R1)
from its room temperature value, over the specified temperature
range. Generally used for by-passing (decoupling), coupling,
filtering, frequency discrimination, DC blocking and voltage transient
suppression with greater volumetric efficiency than Class l units,
whilst maintaining stability within defined limits.
Capacitance and dissipation factor are affected by:-
Time
(Ageing)
Voltage
(AC or DC)
Frequency
4
Multilayer
Summary
Ceramic
Capacitors
Technical
Dielectric Characteristics
C0G
Dielectric
classification
CECC
EIA
MIL
Rated temperature
range
Maximum capacitance
change over
temperature range
No DC voltage applied
Rated DC voltage applied
Syfer dielectric
ordering code
C
0 ± 30 ppm/°C
±20%
+20-30%
R
±15%
-
X
< 0.025
±15%
+15-25%
-50
Typical Dielectric Temperature Characteristics
X7R
Stable
50
C0G Capacitance Vs Temperature
Ultra stable
1B/CG
COG(NPO)
CG(BP)
-55°C to +125°C
BZ
2C1
2R1
X7R
2X1
UPPER LIMIT
-55°C to +125°C
∆C
ppm/°C
BX
25
TYPICAL LIMIT
0
-25
LOWER LIMIT
B
-55
-25
0
25
50
75
100
125
Tangent of loss angle
Cr > 50pF < 0.0015
(tan
δ
)
Cr < 50pF = 0.0015 (15 +0.7)
Cr
Insulation resistance
(Ri)
Time constant (Ri X Cr)
(whichever is the less)
Capacitance
tolerance
100G
Ω
or
1000s
Cr < 10pF ± 0.10pF
± 0.25pF
± 0.50pF
± 1.0pF
Cr > 10pF ± 1%
± 2%
± 5%
± 10%
(B)
(C)
(D)
(F)
(F)
(G)
(J)
(K)
Temperature (°C)
X7R Capacitance Vs Temperature
100G
Ω
or
1000s
± 5% (J)
± 10% (K)
± 20% (M)
20
% Capacitance Change
10
UPPER LIMIT
TYPICAL
LIMIT
0
Dielectric strength
16-200V
>200V <500V
500V/630V
>1kV
Climatic category
(IEC)
Chip
Moulded
Dipped
Discoidal
Ageing characteristic
(Typical)
Approvals
Chip
Moulded radial
Dipped radial
Voltage applied for 5 seconds.
Charging current limited to 50 mA maximum.
2.5 times
Rated voltage + 250V
1.5 times
1.25 times
2.5 times
Rated voltage + 250V
1.5 times
1.25 times
-10
LOWER LIMIT
-20
-55
-30
-5
20
45
70
95
120
Temperature (°C)
55/125/56
55/125/56
55/125/21
55/125/56
55/125/56
55/125/56
55/125/21
55/125/56
Power Ratings for COG and X7R
CECC 32 101 801
CECC 30 601 009
CECC 30 601 008
CECC 32 101 801
CECC 30 701 007
CECC 30 701 013
Power (mW)
Zero
1% per time decade
Operating Temperature (°C)
5
Multilayer
Summary
Ceramic
Capacitors
Technical
Capacitance vs Frequency - 10nF chip
Ultra Stable C0G dielectric
100
Impedance vs Frequency - chips
Ultra Stable C0G dielectric
1000000
100000
10pF
100pF
1nF
10nF
Change in Capacitance (%)
80
60
40
20
0
-20
0.0001
Impedance (ohms)
10000
1000
100
10
1
0.1
0.001
0.01
0.1
1
10
100
0.01
0.0001 0.001 0.01
0.1
1
10
100
1000 10000
Frequency (MHz)
Stable X7R dielectric
100
Frequency (MHz)
Stable X7R dielectric
1000000
100000
1nF
10nF
100nF
1µF
Change in Capacitance (%)
80
60
40
20
0
-20
0.0001
Impedance (ohms)
10000
1000
100
10
1
0.1
0.001
0.01
0.1
1
10
100
0.01
0.0001 0.001 0.01
0.1
1
10
100
1000 10000
Frequency (MHz)
Frequency (MHz)
E.S.R. vs Frequency - chips
Ultra Stable C0G dielectric
100000
10000
1000
10pF
100pF
1nF
10nF
Stable X7R dielectric
100000
10000
1000
1nF
10nF
100nF
1µF
ESR (ohms)
100
10
1
0.1
0.01
0.0001
ESR (ohms)
100
10
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
6
Multilayer
Summary
Ceramic
Capacitors
Technical
Ageing of Ceramic Capacitors
Ageing
Capacitor ageing is a term used to describe the negative,
logarithmic capacitance change which takes place in ceramic
capacitors with time. The crystalline structure for barium titanate
based ceramics changes on passing through its Curie temperature
(known as the Curie Point) at about 125°C. This domain structure
relaxes with time and in doing so, the dielectric constant reduces
logarithmically; this is known as the ageing mechanism of the
dielectric constant.
The more stable dielectrics have the lowest ageing rates.
The ageing process is reversible and repeatable.
Whenever the capacitor is heated to a temperature above the Curie
Point the ageing process starts again from zero.
The ageing constant, or ageing rate, is defined as the percentage
loss of capacitance due to the ageing process of the dielectric which
occurs during a decade of time (a tenfold increase in age) and is
expressed as percent per logarithmic decade of hours. As the law
of decrease of capacitance is logarithmic, this means that in a
capacitor with an ageing rate of 1% per decade of time, the
capacitance will decrease at a rate of:
a)
b)
c)
d)
e)
1% between 1 and 10 hours
An additional 1% between the following 10 and 100 hours
An additional 1% between the following 100 and 1000 hours
An additional 1% between the following 1000 and 10000
hours etc
The ageing rate continues in this manner throughout the
capacitor's life.
Capacitance Measurements
Because of ageing it is necessary to specify an age for referee
measurements at which the capacitance shall be within the prescribed
tolerance. This is fixed at 1000 hours, since for practical purposes
there is not much further loss of capacitance after this time.
All capacitors shipped are within their specified tolerance at the
standard reference age of 1000 hours after having cooled through
their Curie temperature.
The ageing curve for any ceramic dielectric is a straight line when
plotted on semi-log paper.
Capacitance vs Time - Ageing
Typical values of the ageing constant for our Multilayer Ceramic
Capacitors are:
1
10
100
1000
10000
∆c
%
Dielectric class
Ultra Stable C0G
Stable X7R
Typical agreed value
Negligible capacitance loss
through ageing
1% per decade of time
Age (Hours)
Summary and Conclusions
1.0
The recommended sequence of testing Multilayer Ceramic
Capacitors is as follows:
a) Capacitance.
Applying factors based on the
manufacturer's ageing rate and the time elapsed since the last
Curie temperature excursion.
b) Dissipation factor
c) Voltage proof test
d) Insulation resistance
e) Other tests.
If any limits are specified for change in
capacitance during a long term test (life test, for example),
the capacitor should be de-aged before both initial and final
measurements. De-ageing is accomplished by exposure of
the capacitors to 150°C for 1 hour (without voltage) and
stabilised at room temperature for 24 hours before
capacitance measurements are made.
2.0
The ageing process is completely repeatable and
predictable for a given capacitor.
3.0
Capacitance change is negative and logarithmic in respect to
time.
4.0
Class C0G dielectric has a negligible ageing rate.
5.0
Class 2 ceramic dielectrics have ageing rates which will vary
from 0.8 to 8%, dependent upon particular ceramic
composition employed. This wide capacitance change, as a
result of ‘shelf’ ageing and temperature cycling, illustrates why
close-tolerance (less than ±5%) high dielectric constant
ceramics should not be specified.
6.0
Soldering both leaded and chip class 2 capacitors into a circuit
will, because of the ageing phenomenon, give a temporary
increase in capacitance value. The magnitude of this change
will be dependent on the soldering temperature, time and
dielectric class.
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stm32/stm8
