Integrated Device Technology, Inc.
ICS1893CF
General
The ICS1893CF is a low-power, physical-layer device (PHY)
that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.
The ICS1893CF is intended for MII, Node applications that
require the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
The ICS1893CF incorporates Digital-Signal Processing (DSP)
control in its Physical-Medium Dependent (PMD) sub layer. As
a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100MHz. With this ICS-patented
technology, the ICS1893CF can virtually eliminate errors from
killer packets.
The ICS1893CF provides a Serial-Management Interface for
exchanging command and status information with a
Sta t i o n - M a n a g e m e n t ( S TA) e n t i t y. T h e I CS 1 8 9 3 C F
Media-Dependent Interface (MDI) can be configured to
provide either half- or full-duplex operation at data rates of 10
Mb/s or 100Mb/s.
The ICS1893CF is available in a 300-mil 48-lead SSOP
pa c k ag e. T he I CS 18 9 3C F s h ar es t he s a m e p r o v en
performance circuitry with the ICS1893BF and is a pin-for-pin
replacement of the 1893BF.
Document Type:
Document Stage:
Data Sheet
Rev. K Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
Features
•
Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
•
•
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Single-chip, fully integrated PHY provides PCS, PMA, PMD,
and AUTONEG sub layers functions of IEEE standard.
10Base-T and 100Base-TX IEEE 8802.3 compliant
Single 3.3V power supply
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
– Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 400 mW)
Power-Down mode typically 21mW
Clock and crystal supported
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Small footprint 48-pin 300 mil. SSOP package
Also available in small footprint 56-pin 8x8 MLF2 package
Available in Industrial Temp
•
•
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Applications:
NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
•
•
•
ICS1893CF Block Diagram
100Base-T
10/100 MII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
ICS1893CF, Rev. K, 05/13/10
IDT reserves the right to make changes in the device data identified in
this publication without further notice. IDT advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
May, 2010
ICS1893CF Data Sheet - Release
Revision History
Revision History
•
•
•
•
•
•
•
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Initial preliminary release of this document, Rev A, dated July 10, 2006.
Rev B – remove all references to ICS1893CK; removed package drawing and ordering info.
Rev C – added CK package and ordering information back to datasheet; removed TOC.
Rev E – changed resistor values in table 9.3 and on Figure 9-1, “ICS1893CF 10TCSR and 100TCSR”.
Rev G – added top side marking for 1893CKILF.
Rev H – updated hex numerology in table 7-9.
Rev J, 8/11/09 – added EOL note for ordering information per PDN U-09-01.
Rev K, 5/13/10 – removed non-green parts ordering information per PDN U-09-01.
ICS1893CF, Rev. K, 05/13/10
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
2
May, 2010
ICS1893CF Data Sheet Rev. J - Release
Chapter 1 Abbreviations and Acronyms
Chapter 1
Abbreviations and Acronyms
Table 1-1
lists and interprets the abbreviations and acronyms used throughout this data sheet.
Table 1-1.
Abbreviations and Acronyms
Interpretation
4-Bit / 5-Bit Encoding/Decoding
American National Standards Institute
complimentary metal-oxide semiconductor
Carrier Sense Multiple Access with Collision Detection
Command Override Write
digital signal processing
End-of-Stream Delimiter
Fiber Distributed Data Interface
frequency-locked loop
Fast Link Pulse
A ‘dead’ time on the link following a 10Base-T packet, not to be confused with idle
International Electrotechnical Commission
Institute of Electrical and Electronic Engineers
International Standards Organization
Latching High
Latching Low
Latching Maximum
Media Access Control
maximum
Megabits per second
Media Dependent Interface
Media Independent Interface Crossed
Management Frame
Media Independent Interface
minimum
Multi-Level Transition Encoding (3 Levels)
Not Applicable
Normal Link Pulse
Number
Not Return to Zero
Not Return to Zero, Invert on one
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
3
May, 2010
Abbreviation /
Acronym
4B/5B
ANSI
CMOS
CSMA/CD
CW
DSP
ESD
FDDI
FLL
FLP
IDL
IEC
IEEE
ISO
LH
LL
LMX
MAC
Max.
Mbps
MDI
MDIX
MF
MII
Min.
MLT-3
N/A
NLP
No.
NRZ
NRZI
ICS1893CF, Rev. K, 05/13/10
ICS1893CF Data Sheet - Release
Chapter 1 Abbreviations and Acronyms
Table 1-1.
Abbreviations and Acronyms (Continued)
Interpretation
Open Systems Interconnection
Organizationally Unique Identifier
Physical Coding sublayer
physical-layer device
The ICS1893CF is a physical-layer device, also referred to as a ‘PHY’ or ‘PHYceiver’.
(The ICS1890 is also a physical-layer device.)
phase-locked loop
Physical Medium Attachment
Physical Medium Dependent
parts per million
read only
read/write
read/write zero
self-clearing
Special Functions
Start-of-Frame Delimiter
Stream Interface, Serial Interface, or Symbol Interface.
With reference to the MII/SI pin, the acronym ‘SI’ has multiple meanings.
•
Generically, SI means 'Stream Interface', and is documented as such in this data
sheet.
•
However, when the MAC Interface is configured for:
– 10M operations, SI is an acronym for 'Serial Interface'.
– 100M operations, SI is an acronym for 'Symbol Interface'.
Signal Quality Error
Start-of-Stream Delimiter
Small Shrink Outline Package
Station Management Entity
shielded twisted pair
Technology Ability Field
Twisted-Pair Physical Layer Medium Dependent
typical
unshielded twisted pair
Abbreviation /
Acronym
OSI
OUI
PCS
PHY
PLL
PMA
PMD
ppm
RO
R/W
R/W0
SC
SF
SFD
SI
SQE
SSD
SSOP
STA
STP
TAF
TP-PMD
Typ.
UTP
ICS1893CF, Rev. K, 05/13/10
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
4
May, 2010
ICS1893CF Data Sheet Rev. J - Release
Chapter 2 Conventions and Nomenclature
Chapter 2
Conventions and Nomenclature
Table 2-1
lists and explains the conventions and nomenclature used throughout this data sheet.
Table 2-1.
Bits
Conventions and Nomenclature
Item
Convention / Nomenclature
•
A bit in a register is identified using the format ‘register.bit’. For example, bit
•
•
0.15 is bit 15 of register 0.
When a colon is used with bits, it indicates the range of bits. For example,
bits 1.15:11 are bits 15, 14, 13, 12, and 11 of register 1.
For a range of bits, the order is always from the most-significant bit to the
least-significant bit.
Code groups
Colon (:)
Within this table, see the item ‘Symbols’
Within this table, see these items:
•
‘Bits’
•
‘Pin (or signal) names’
Numbers
•
As a default, all numbers use the decimal system (that is, base 10) unless
•
Pin (or signal) names
followed by a lowercase letter. A string of numbers followed by a lowercase
letter:
– A ‘b’ represents a binary (base 2) number
– An ‘h’ represents a hexadecimal (base 16) number
– An ‘o’ represents an octal (base 8) number
All numerical references to registers use decimal notation (and not
hexadecimal).
•
All pin or signal names are provided in capital letters.
•
A pin name that includes a forward slash ‘/’ is a multi-function, configuration
pin. These pins provide the ability to select between two ICS1893CF
functions. The name provided:
– Before the ‘/’ indicates the pin name and function when the signal level
on the pin is logic zero.
– After the ‘/’ indicates the pin name and function when the signal level on
the pin is logic one.
For example, the HW/SW pin selects between Hardware (HW) mode and
Software (SW) mode. When the signal level on the HW/SW pin is logic:
– Zero, the ICS1893CF Hardware mode is selected.
– One, the ICS1893CF Software mode is selected.
•
An ‘n’ appended to the end of a pin name or signal name (such as
RESETn) indicates an active-low operation.
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When a colon is used with pin or signal names, it indicates a range. For
example, TXD[3:0] represents pins/signals TXD3, TXD2, TXD1, and TXD0.
•
When pin name abbreviations are spelled out, words in parentheses
indicate additional description that is not part of the pin name abbreviation.
Registers
•
A bit in a register is identified using the format ‘register.bit’. For example, bit
•
•
0.15 is bit 15 of register 0.
All numerical references to registers use decimal notation (and not
hexadecimal).
When register name abbreviations are spelled out, words in parentheses
indicate additional description that is not part of the register name
abbreviation.
ICS1893CF, Rev. K, 05/13/10
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
5
May, 2010
