1EDN7550 and 1EDN8550
Single-channel EiceDRIVER
™
with true differential inputs
Feature list
•
•
•
•
•
Single-channel non-isolated gate-drive IC with true differential inputs
Very large common-mode input voltage range (CMR) up to ± 150 V (Table
1)
Supply voltage (V
DD
) up to 20 V
2 UVLO options: 4 V and 8 V
Separate low impedance source and sink outputs
- 4 A / 0.85 Ω source
- 8 A / 0.35 Ω sink
45 ns propagation delay with -7 / +10 ns accuracy
SOT23 6-pin package
Fully qualified for industrial applications according to JEDEC
•
•
•
Description
1EDNx550 is a new family of single-channel non-isolated gate-driver ICs. Due to the unique fully differential
input circuitry with excellent common-mode rejection, the logic driver state is exclusively controlled by the
voltage difference between the two inputs, completely independent of the driver’s reference (ground) potential.
This eliminates the risk for wrong triggering and thus is a significant benefit in all applications exhibiting
voltage differences between driver and controller ground, a problem typical for systems with
•
4-pin packages (Kelvin Source connection)
• high parasitic PCB inductances (long distances, single-layer PCB)
• bipolar gate drive
In addition, within the allowed common-mode voltage range, CMR (Table
1),
1EDNx550 allows to address even
high-side applications.
Table 1
Product portfolio
CMR static
+ 72 V / - 84 V
+ 72 V / - 84 V
CMR dynamic
± 150 V
± 150 V
UVLO
4V
8V
Package
PG-SOT23-6
PG-SOT23-6
Orderable Part Number
1EDN7550BXTSA1
1EDN8550BXTSA1
Part number
1EDN7550B
1EDN8550B
1EDNx550
R
in1
DV
Rin
R
in2
SGND
IN+
IN-
GND
VDD
OUT_SRC
OUT_SNK
Z
VDD
R
gon
V
DD
R
goff
C
VDD
Figure 1
Datasheet
Typical application
Please read the Important Notice and Warnings at the end of this document
Rev. 2.0
2018-05-14
www.infineon.com
1EDN7550 and 1EDN8550
Table of contents
Single-channel EiceDRIVER
™
with true differential inputs
Table of contents
Feature list
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
2
3
3.1
3.1.1
3.2
3.3
4
4.1
4.2
4.3
4.4
4.5
5
6
6.1
6.2
6.3
6.4
7
8
Pin configuration and description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common mode input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Supply voltage and Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics and parameters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical applications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switches with Kelvin source connection (4-pin packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Applications with significant parasitic PCB-inductances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switches with bipolar gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High-side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Layout guidelines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package dimensions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Datasheet
2
Rev. 2.0
2018-05-14
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER
™
with true differential inputs
Pin configuration and description
1
Pin configuration and description
The pin configuration for the SOT23 6-pin package is illustrated in
Figure 2;
a description is given in
Table 2
. For
functional details, please read
Chapter 3.
SOT23-6
1
IN-
OUT_SNK
6
2
GND OUT_SRC
5
3
IN+
VDD
4
Figure 2
Table 2
Symbol
IN+
IN-
GND
VDD
OUT_SNK
OUT_SRC
Pin configuration SOT23 6-pin (top side view)
Pin description
Description
Positive input
connected to PWM output of controller via resistor (typically 33 kΩ)
Negative input
connected to controller ground via resistor (typically 33 kΩ)
Ground
negative gate drive voltage ("off" state)
Positive supply voltage
positive gate drive voltage ("on" state)
Driver output sink
low-impedance switch to GND (8 A / 0.35 Ω)
Driver output source
low-impedance switch to VDD (4 A / 0.85 Ω)
Datasheet
3
Rev. 2.0
2018-05-14
1EDN7550 and 1EDN8550
Block diagram
Single-channel EiceDRIVER
™
with true differential inputs
2
Block diagram
A simplified functional block diagram of 1EDNx550 is given in
Figure 3.
VDD
UVLO
IN+
OUT_SRC
Diff. Amp.
+ LPF
Differential
Schmitt
Trigger
Logic
IN-
OUT_SNK
GND
Figure 3
Block diagram
Datasheet
4
Rev. 2.0
2018-05-14
1EDN7550 and 1EDN8550
Functional description
Single-channel EiceDRIVER
™
with true differential inputs
3
Functional description
1EDNx550 is a fast single-channel non-isolated gate driver. However, compared with standard drivers, this new
gate driver family extends the range of possible applications into fields usually reserved for isolated drivers,
thereby generating significant system cost benefits.
The key to make this possible, is moving from the standard ground related to a true differential input with very
high common-mode rejection. The required symmetry of the input circuitry is achieved by on-chip trimming; it
finally allows to deal with peak common-mode voltages of up to ± 150 V between driver reference (GND) and
system ground (SGND). 1EDNx550 is not only ideally suited for any application with unwanted shifts between
driver and system ground, but may also be utilized as a high-side driver within the allowed common-mode
range. Besides, switches requiring a bipolar driving voltage can be operated very easily.
3.1
Differential input
Figure 4
depicts the signal path from the controller’s PWM output to the logic gate driver signal as implemented
on 1EDNx550.
Controller
VS
0
1EDNx550
R
in1
2kW
IN+
DV
Rin
/ k
IN-
R
in2
15pF
2kW
GND
1kW
15pF
1kW
A
v
= 4.5
PWM
C
p1
DV
Rin
C
p2
12 MHz
2
nd
order
Lowpass
Differential
Schmitt
Trigger
Pulse
Extender
SGND
k = (R
in
[kW] + 3) / 3
Figure 4
1EDNx550 input signal path
The controller output signal, switching between controller supply VS and zero, is applied at the one leg of a
differential voltage divider, while the other is connected to the controller ground SGND. The divider ratio has to
be adapted to VS to allow a fixed Schmitt-Trigger threshold voltage. For VS = 3.3 V,
R
in1
and
R
in2
are chosen to be
33 kΩ, resulting in a static divider ratio of k = 12 at the driver inputs and 36 at the internal voltage amplifier. With
VS other than 3.3 V,
R
in
has to fulfil the relation:
R
in1
=
R
in2
= 10.9 VS − 3 kΩ
Amplified by a factor of 4.5, the signal is filtered by a 2
nd
order low-pass filter. Taking into account the RC filter in
front of the amplifier, the overall input path exhibits the frequency behavior of a 3
rd
order low-pass filter with a
corner frequency around 12 MHz. The suppression of high frequencies is important for two reasons. Inductive
common-mode ringing in fast-switching power systems is typically in the 100 MHz and above range and thus is
effectively damped. The high-frequency symmetry of the voltage divider is influenced by parasitic capacitances,
particularly
C
p1
and
C
p2
, the parallel capacitances of
R
in1
and
R
in2
. They are typically in the 50 to 100 fF range,
rather independent of resistor size. Without filtering, any asymmetry would translate high-frequency common-
mode into differential signals.
The filtered signal is then applied to a differential Schmitt-Trigger with accurate trimmed threshold levels and
converted to the logic switch control signal. The subsequent pulse extender function guarantees that no pulses
shorter than 25 ns are transmitted to the output, thereby further improving noise immunity.
Due to the filtering requirements the input-to-output propagation delay is slightly increased to around 45 ns. By
means of on-chip trimming, however, the usually more relevant propagation delay variation can still be kept
low at +10 / -7 ns.
Datasheet
5
Rev. 2.0
2018-05-14
