General Configuration Timing Specifications............................................................................................................... 104
POR Specifications..................................................................................................................................................105
AS Configuration Timing.......................................................................................................................................... 107
Configuration Bit Stream Sizes................................................................................................................................. 112
Document Revision History for the Intel Stratix 10 Device Datasheet...................................................................................... 118
Intel
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®
10 Device Datasheet
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Intel
®
Stratix
®
10 Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for
Intel
®
Stratix
®
10 devices.
Table 1.
Intel Stratix 10 Device Grades and Speed Grades Supported
Device Grade
Extended
•
•
•
•
•
•
•
•
•
•
•
–E1V (fastest)
–E2V
–E2L
–E3V
–E3X
–I1V
–I2V
–I2L
–I3V
–I3X
–C2L
Speed Grade Supported
Industrial
Commercial
The suffix after the speed grade denotes the power options offered in Intel Stratix 10 devices.
•
•
•
V—SmartVID with standard static power. For “V” suffix devices, both V
CC
and V
CCP
must share the same SmartVID
regulator. V
CCL_HPS
can share the same SmartVID regulator or can use a separate fixed voltage regulator.
L—0.85 V fixed voltage with low static power
X—0.85 V fixed voltage with lowest static power
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of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before
relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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®
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®
10 Device Datasheet
683181 | 2022.01.12
Table 2.
Datasheet Status for Intel Stratix 10 Devices
Variant
Intel Stratix 10 GX
Intel Stratix 10 SX
Intel Stratix 10 TX
Intel Stratix 10 MX
Intel Stratix 10 DX
Datasheet Status
Final (Preliminary for 1SG040HF35 device only)
Final (Preliminary for 1SX040HF35 device only)
Final
Final
Final
(1)
Note:
The
H-Tile Transmitter Specifications
table is still preliminary.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel Stratix 10 devices.
Operating Conditions
Intel Stratix 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Intel Stratix 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel Stratix 10 devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
Caution:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
(1)
Specifications related to Intel Intellectual Property (IP) products, UPI IP, and DDR-T IP are preliminary.
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®
Stratix
®
10 Device Datasheet
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Table 3.
Absolute Maximum Ratings for Intel Stratix 10 Devices
Symbol
Description
Core voltage power supply
Periphery circuitry and transceiver fabric interface power supply
Embedded memory and digital transceiver power supply
Power supply for programmable regulator and I/O pre-driver
Battery back-up power supply for design security volatile key register
Configuration pins power supply
I/O buffers power supply (except for 1SG040HF35 and 1SX040HF35
banks 3C and 3D)
I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices
bank 3C only
I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices
bank 3D only
Phase-locked loop (PLL) analog power supply
Secure Device Manager (SDM) block PLL digital power supply
SDM block PLL analog power supply
Fuse block writing power supply
ADC voltage sensor power supply
Power supply for the Universal Interface Bus between the core and
embedded HBM2 memory
Power supply for the embedded HBM2 memory
Transmitter analog power supply
Receiver analog power supply
Transmitter output buffer power supply
Condition
—
—
—
—
—
—
3 V I/O
LVDS I/O
—
—
—
—
—
—
—
—
—
—
—
—
(2)
Minimum
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.30
–0.30
–0.50
–0.50
–0.50
Maximum
1.26
1.26
1.24
2.46
2.46
2.19
4.10
2.19
3.63
1.98
2.46
1.21
2.19
3.19
2.19
1.50
3.00
1.47
1.47
2.46
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
continued...
V
CC
V
CCP
V
CCERAM
V
CCPT
V
CCBAT
V
CCIO_SDM
V
CCIO
V
CCIO3C
V
CCIO3D
V
CCA_PLL
V
CCPLLDIG_SDM
V
CCPLL_SDM
V
CCFUSEWR_SDM
V
CCADC
V
CCIO_UIB
V
CCM_WORD
V
CCT_GXB
V
CCR_GXB
V
CCH_GXB
(2)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
