Intel
®
Stratix
®
10 GX/SX Device
Overview
Subscribe
Send Feedback
S10-OVERVIEW | 2019.02.15
Latest document on the web:
PDF
|
HTML
Contents
Contents
1. Intel
®
Stratix
®
10 GX/SX Device Overview.................................................................... 3
1.1. Intel Stratix 10 GX/SX Family Variants.....................................................................4
1.1.1. Available Options....................................................................................... 6
1.2. Innovations in Intel Stratix 10 FPGAs and SoCs......................................................... 6
1.3. FPGA and SoC Features Summary...........................................................................8
1.4. Intel Stratix 10 Block Diagram............................................................................... 11
1.5. Intel Stratix 10 FPGA and SoC Family Plan..............................................................11
1.6. Intel Hyperflex Core Architecture........................................................................... 14
1.7. Heterogeneous 3D SiP Transceiver Tiles.................................................................. 15
1.8. Intel Stratix 10 Transceivers................................................................................. 16
1.8.1. PMA Features......................................................................................... 17
1.8.2. PCS Features..........................................................................................19
1.9. PCI Express Gen1/Gen2/Gen3 Hard IP................................................................... 20
1.10. Interlaken PCS Hard IP...................................................................................... 20
1.11. 10G Ethernet Hard IP........................................................................................ 21
1.12. External Memory and General Purpose I/O........................................................... 21
1.13. Adaptive Logic Module (ALM).............................................................................. 22
1.14. Core Clocking................................................................................................... 23
1.15. Fractional Synthesis PLLs and I/O PLLs.................................................................24
1.16. Internal Embedded Memory................................................................................24
1.17. Variable Precision DSP Block............................................................................... 24
1.18. Hard Processor System (HPS)............................................................................. 27
1.18.1. Key Features of the Intel Stratix 10 HPS...................................................28
1.19. Power Management........................................................................................... 31
1.20. Device Configuration and Secure Device Manager (SDM)......................................... 31
1.21. Device Security..................................................................................................33
1.22. Configuration via Protocol Using PCI Express..........................................................33
1.23. Partial and Dynamic Reconfiguration.................................................................... 34
1.24. Fast Forward Compile......................................................................................... 34
1.25. Single Event Upset (SEU) Error Detection and Correction........................................34
1.26. Document Revision History for the Intel Stratix 10 GX/SX Device Overview................35
Intel
®
Stratix
®
10 GX/SX Device Overview
2
Send Feedback
S10-OVERVIEW | 2019.02.15
Send Feedback
1. Intel
®
Stratix
®
10 GX/SX Device Overview
Intel’s 14 nm Intel
®
Stratix
®
10 GX FPGAs and SX SoCs deliver 2X the core
performance and up to 70% lower power over previous generation high-performance
FPGAs.
Featuring several groundbreaking innovations, including the all new Intel Hyperflex
™
core architecture, this device family enables you to meet the demand for ever-
increasing bandwidth and processing performance in your most advanced applications,
while meeting your power budget.
With an embedded hard processor system (HPS) based on a quad-core 64 bit ARM
®
Cortex
®
-A53, the Intel Stratix 10 SoC devices deliver power efficient, application-class
processing and allow designers to extend hardware virtualization into the FPGA fabric.
Intel Stratix 10 SoC devices demonstrate Intel's commitment to high-performance
SoCs and extend Intel's leadership in programmable devices featuring an ARM-based
processor system.
Important innovations in Intel Stratix 10 FPGAs and SoCs include:
•
•
•
•
•
•
•
•
•
•
•
•
All new Intel Hyperflex core architecture delivering 2X the core performance
compared to previous generation high-performance FPGAs
Industry leading Intel 14 nm tri-gate (FinFET) technology
Heterogeneous 3D System-in-Package (SiP) technology
Monolithic core fabric with up to 2.8 million logic elements (LEs)
Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver
tiles
Transceiver data rates up to 28.3 Gbps chip-to-chip/module and backplane
performance
M20K (20 kbit) internal SRAM memory blocks
Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops
(PLLs)
Hard PCI Express
®
Gen3 x16 intellectual property (IP) blocks
Hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) in every
transceiver channel
Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
Hard fixed-point and IEEE 754 compliant hard floating-point variable precision
digital signal processing (DSP) blocks with up to 10 TFLOPS compute performance
with a power efficiency of 80 GFLOPS per Watt
Quad-core 64 bit ARM Cortex-A53 embedded processor running up to 1.5 GHz in
SoC family variants
Programmable clock tree synthesis for flexible, low power, low skew clock trees
•
•
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
1. Intel
®
Stratix
®
10 GX/SX Device Overview
S10-OVERVIEW | 2019.02.15
•
Dedicated secure device manager (SDM) for:
—
—
—
—
Enhanced device configuration and security
AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and
authentication
Multi-factor authentication
Physically Unclonable Function (PUF) service and software programmable
device configuration capability
•
•
Comprehensive set of advanced power saving features delivering up to 70% lower
power compared to previous generation high-performance FPGAs
Non-destructive register state readback and writeback, to support ASIC
prototyping and other applications
With these capabilities, Intel Stratix 10 FPGAs and SoCs are ideally suited for the most
demanding applications in diverse markets such as:
•
•
•
•
•
•
•
•
•
Compute and Storage—for
custom servers, cloud computing and data center
acceleration
Networking—for
Terabit, 400G and multi-100G bridging, aggregation, packet
processing and traffic management
Optical Transport Networks—for
OTU4, 2xOTU4, 4xOTU4
Broadcast—for
high-end studio distribution, headend encoding/decoding, edge
quadrature amplitude modulation (QAM)
Military—for
radar, electronic warfare, and secure communications
Medical—for
diagnostic scanners and diagnostic imaging
Test and Measurement—for
protocol and application testers
Wireless—for
next-generation 5G networks
ASIC Prototyping—for
designs that require the largest monolithic FPGA fabric
with the highest I/O count
1.1. Intel Stratix 10 GX/SX Family Variants
Intel Stratix 10 devices are available in FPGA (GX) and SoC (SX) variants.
•
Intel Stratix 10 GX
devices deliver up to 1 GHz core fabric performance and
contain up to 2.8 million LEs in a monolithic fabric. They also feature up to 96
general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4
external memory interface performance. The transceivers are capable of up to
28.3 Gbps short reach and across the backplane. These devices are optimized for
FPGA applications that require the highest transceiver bandwidth and core fabric
performance, with the power efficiency of Intel’s industry-leading 14 nm tri-gate
process technology.
Intel Stratix 10 SX
devices have a feature set that is identical to Intel Stratix 10
GX devices, with the addition of an embedded quad-core 64 bit Arm* Cortex A53
hard processor system.
•
Intel
®
Stratix
®
10 GX/SX Device Overview
4
Send Feedback
1. Intel
®
Stratix
®
10 GX/SX Device Overview
S10-OVERVIEW | 2019.02.15
Common to all Intel Stratix 10 family variants is a high-performance fabric based on
the new Intel Hyperflex core architecture that includes additional Hyper-Registers
throughout the interconnect routing and at the inputs of all functional blocks. The core
fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module
(ALM) and a rich set of high performance building blocks including:
•
•
•
•
•
M20K (20 kbit) embedded memory blocks
Variable precision DSP blocks with hard IEEE 754 compliant floating-point units
Fractional synthesis and integer PLLs
Hard memory controllers and PHY for external memory interfaces
General purpose IO cells
To clock these building blocks, Intel Stratix 10 devices use programmable clock tree
synthesis, which uses dedicated clock tree routing to synthesize only those branches
of the clock trees required for the application. All devices support in-system, fine-
grained partial reconfiguration of the logic array, allowing logic to be added and
subtracted from the system while it is operating.
All family variants also contain high speed serial transceivers, containing both the
physical medium attachment (PMA) and the physical coding sublayer (PCS), which can
be used to implement a variety of industry standard and proprietary protocols. In
addition to the hard PCS, Intel Stratix 10 devices contain multiple instantiations of PCI
Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane
configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The
hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power,
and increase your productivity.
Send Feedback
Intel
®
Stratix
®
10 GX/SX Device Overview
5
电机驱动控制（Motor Control）
