24LC08
8K-Bit Serial EEPROM
OVERVIEW
The 24LC08 serial EEPROM has a 8,192-bit (1,024-byte) capacity, supporting the standard I C -bus
serial interface. It is fabricated using CERAMATE's most advanced CMOS technology. One of its major’ feature
is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection
is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to
16 bytes of data into the EEPROM in a single write operation. Another significant feature of the 24LC08
is its support for fast mode and standard mode.
2
TM
FEATURES
I
2
C-Bus Interface
•
•
Two-wire serial interface
Automatic word address increment
Operating Characteristics
•
Operating voltage
— 2.5 V to 5.5 V (write)
— 2.2 V to 5.5 V (read)
EEPROM
•
•
•
•
•
•
•
8K-bit (1,024-byte)
storage area
16-byte page buffer
Typical 3.5 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
•
•
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200
µA
at 5.5 V
— Maximum stand-by current: < 5
µA
at 3.3 V
•
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
•
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 3,000 V (HBM)
— 300 V (MM)
Packages
ORDERING INFORMATION
•
24 LC
8-pin DIP, SOP, and TSSOP
08 X
X
Operating Voltage
LC:2.5~5.5V,CMOS
Type
08=8K
Temp. grade
Blank:-25℃~+70℃
Packing
Blank :Tube
A :Taping(SOP8)
T :Taping(TSSOP8)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 1 of 23
Rev 1.1 Nov. 18, 2002
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24LC08
8K-Bit Serial EEPROM
SDA
Start/Stop
Logic
HV Generation
Timing Control
WP
Control Logic
SCL
EEPROM
Cell Array
Slave Address
Comparator
Word Address
Pointer
Row
decoder
1024 x 8 bits
A0
A1
A2
Column Decoder
Data Register
D
OUT
and ACK
Figure 3-1. 24LC08 Block Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 2 of 23
Rev 1.1 Nov. 18, 2002
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24LC08
8K-Bit Serial EEPROM
V
CC
WP
SCL SDA
24LC08
A0
A1
A2
V
SS
NOTE:
The 24LC08 is available
in 8-pin DIP, SOP, and TSSOP package.
Figure 3-2. Pin Assignment Diagram
Table 3-1. 24LC08 Pin Descriptions
Name
A0, A1, A2
V
SS
SDA
Type
Input
–
I/O
Description
Input pins for device address selection. To configure a device address,
these pins should be connected to the V
CC
or V
SS
of the device.
Ground pin.
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to V
CC.
Typical values for this pull-up resistor are 4.7 kΩ
(100 kHz) and 1 kΩ (400 kHz).
Schmitt trigger input pin for serial clock input.
Input pin for hardware write protection control. If you tie this pin to V
CC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to V
SS
, the write function is enabled.
Single power supply.
Circuit
Type
1
–
3
SCL
WP
Input
Input
2
1
V
CC
–
–
NOTE:
See the following page for diagrams of pin circuit types 1, 2, and 3.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 3 of 23
Rev 1.1 Nov. 18, 2002
Fax:886-3-3521052
24LC08
8K-Bit Serial EEPROM
A0, A1,
A2, WP
SCL
Noise
Filter
Figure 3-3. Pin Circuit Type 1
Figure 3-4. Pin Circuit Type 2
SDA
Data Out
V
SS
Noise
Filter
Data In
Figure 3-5. Pin Circuit Type 3
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 4 of 23
Rev 1.1 Nov. 18, 2002
Fax:886-3-3521052
24LC08
8K-Bit Serial EEPROM
FUNCTION DESCRIPTION
I C-BUS INTERFACE
2
The 24LC08 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of
a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to
V
CC
by a pull-up resistor that is located somewhere on the bus.
2
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to two 24LC08 devices can be
2
connected to the same I C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter
or receiver, but the master device determines which bus operating mode would be active.
V
CC
V
CC
R
R
SDA
SCL
Slave 1
Bus Master
(Transmitter/
Receiver)
MCU
To V
CC
or V
SS
To V
CC
or V
SS
24LC08
Tx/Rx
A0 A1 A2
Slave 2
24LC08
Tx/Rx
A0 A1 A2
NOTES:
1.
The A0, A1 do not affect the device address of the 24LC08.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I
2
C-Bus)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 5 of 23
Rev 1.1 Nov. 18, 2002
Fax:886-3-3521052
