Obsolete Device
24LC09
8K 2.5V ACR Serial EEPROM
Features
• Supports ACR riser card specification
- 2-wire ACR serial bus interface
- Address:
1011
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 500 nA standby current typical at 5V
• Organized as four blocks of 256 bytes
(4 x 256 x 8)
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 400 kHz Capability (2.5 to 5.5 Volts)
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP, 8-lead SOIC packages
• Available temperature ranges:
- Industrial (I):
-40°C to
+85°C
Package Types
PDIP/SOIC
A0
A1
A2
V
SS
1
2
3
4
24LC09
8
7
6
5
V
CC
WP
SCL
SDA
Block Diagram
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM ARRAY
(2 x 256 x 8) or
(4 x 256 x 8)
PAGE LATCHES
SDA
SCL
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
Description
The Microchip Technology Inc. 24LC09 is an 8 Kbit
Electrically Erasable PROM (EEPROM) designed to
meet the Advanced Communication Riser Special
Interest Group (ACR-SIG). The device is organized as
four blocks of 256 x 8-bit memory that supports the 2-
wire serial interface with a special address:
1011.
Low
voltage design permits operation down to 2.5 volts with
typical standby and active currents of only 5 µA and
1 mA, respectively. The 24LC09 also has a page-write
capability for up to 16 bytes of data. The 24LC09 is
available in the standard 8-pin DIP, 8-lead surface
mount SOIC packages.
I
2
C is a registered trademark of Philips Corporation.
2004 Microchip Technology Inc.
DS21675B-page 1
24LC09
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs, w.r.t. V
SS
....................................................................................................... -0.3V to V
CC
+ 1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-65°C to +125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
†Notice:
Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
1.1
DC Characteristics
Industrial (I):
Characteristic
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger
Inputs
Low level output voltage
Input leakage current
Output leakage current
Min.
.7 V
CC
—
.05 V
CC
—
-10
-10
—
—
—
Standby current
—
—
Max.
—
.3 V
CC
—
.40
10
10
10
3
1
1
1
T
AMB
= -40°C to +85°C
Units
V
V
V
V
µA
µA
pF
mA
mA
µA
µA
(Note)
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= 0.1V to V
CC
V
OUT
= 0.1V to V
CC
V
CC
= 5.0V, T
AMB
= 25°C,
F
CLK
= 1 MHz (Note)
V
CC
= 5.5V,
SCL = 400 kHz
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
WP = V
SS
Test Conditions
DS Characteristics
Param.
No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Sym
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
Pin capacitance
(all inputs/outputs)
I
CC
W
RITE
Operating current
I
CC
R
EAD
I
CCS
Note:
This parameter is periodically sampled and not 100% tested.
DS21675B-page 2
2004 Microchip Technology Inc.
24LC09
1.2
AC Characteristics
Industrial (I):
Parameter
Min
Max
AC Characteristics
Param.
No.
Sym
T
AMB
= -40°C to +85°C
Units
Conditions
1
2
3
4
5
6
7
8
9
10
11
12
F
CLK
T
HIGH
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
—
—
600
1300
—
—
600
600
0
100
600
—
1300
400
100
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (Note
1)
(Note
1)
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
(Note
2)
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
T
LOW
T
R
T
F
T
HD
:
STA
START condition hold time
T
SU
:
STA
START condition setup time
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
T
SU
:
STO
STOP condition setup time
T
AA
T
BUF
Output valid from clock
(Note 2)
Bus free time: Time the bus
must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
13
14
15
16
T
OF
T
SP
T
WC
20+0.1C
B
—
—
1M
250
50
5
—
ns
ns
ms
cycles
2.5V
≤
V
CC
≤
5.5V (Note
1)
(Notes
1 and 3)
25°C, V
CC
= 5.0V, Block Mode
(Note
4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website.
2004 Microchip Technology Inc.
DS21675B-page 3
24LC09
FIGURE 1-1:
BUS TIMING START/STOP
D3
SCL
7
SDA
6
10
START
STOP
FIGURE 1-2:
BUS TIMING DATA
5
3
SCL
7
6
SDA
IN
14
11
SDA
OUT
6
2
4
8
9
10
11
12
DS21675B-page 4
2004 Microchip Technology Inc.
24LC09
2.0
PIN DESCRIPTIONS
This feature allows the user to use the 24LC09 as a
serial ROM when WP is enabled (tied to V
CC
).
The descriptions of the pins are listed in Table 2-1.
2.4
TABLE 2-1:
Name
V
SS
SDA
SCL
WP
V
CC
A0, A1, A2
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
A0, A1, A2
PIN FUNCTION TABLE
Function
These pins are not used by the 24LC09. They may be
left floating or tied to either V
SS
or V
CC
.
3.0
FUNCTIONAL DESCRIPTION
2.1
Serial Address/Data Input/Output
(SDA)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
The 24LC09 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the Start and Stop conditions, while the 24LC09 works
as slave. Both, master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a start or stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
2.2
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.3
Write Protect (WP)
4.1
Bus not Busy (A)
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
Both data and clock lines remain High.
4.2
Start Data Transfer (B)
A High to Low transition of the SDA line while the clock
(SCL) is high determines a start condition. All com-
mands must be preceded by a start condition.
FIGURE 4-1:
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc.
DS21675B-page 5
