24AA64F/24LC64F/24FC64F
64K I
2
C™ Serial EEPROM with Quarter-Array Write-Protect
Device Selection Table
Part
Number
24AA64F
24LC64F
24FC64F
Note 1:
2:
V
CC
Range
1.7-5.5
2.5-5.5
1.7-5.5
Max. Clock
Frequency
400 kHz
(1)
400 kHz
1 MHz
(2)
Temp.
Ranges
I
I, E
I
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA64F/24LC64F/
24FC64F (24XX64F*) is a 64 Kbit Electrically Erasable
PROM. The device is organized as a single block of
8K x 8-bit memory with a 2-wire serial interface. Low-
voltage design permits operation down to 1.7V, with
standby and read currents of only 1
A
and 400
A,
respectively. It has been developed for advanced, low-
power applications such as personal communications
or data acquisition. The 24XX64F also has a page
write capability for up to 32 bytes of data. Functional
address lines allow up to eight devices on the same
bus, for up to 512 Kbits address space. The 24XX64F
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, TDFN and MSOP packages. The
24XX64F is also available in the 5-lead SOT-23
package.
100 kHz for V
CC
<2.5V.
400 kHz for V
CC
<2.5V.
Features:
• Single-Supply with Operation down to 1.7V for
24AA64F/24FC64F Devices, 2.5V for 24LC64F
Devices
• Low-Power CMOS Technology:
- Read current 400
A,
max.
- Standby current 1
A,
max. (I-temp)
• 2-Wire Serial Interface, I
2
C™ Compatible
• Packages with Three Address Pins are
Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 5 ms, typical
• Self-timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-Protect for 1/4 Array
(1800h-1FFFh)
• ESD Protection > 4,000V
• More than One Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available
• Packages include 8-Lead PDIP, SOIC, TSSOP,
MSOP, TDFN, 5-Lead SOT-23
• Pb-Free and RoHS Compliant
Block Diagram
A0 A1 A2 WP
HV
Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
Sense Amp.
R/W Control
Package Types
PDIP/MSOP/SOIC/TSSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
SDA
3
4
V
CC
SCL
V
SS
1
2
SOT-23
5
WP
A0 1
A1 2
A2 3
V
SS
4
TDFN
8 V
CC
7 WP
6 SCL
5 SDA
*24XX64F is used in this document as a generic part number for the 24AA64F/24LC64F/24FC64F devices.
2009-2012 Microchip Technology Inc.
DS22154B-page 1
24AA64F/24LC64F/24FC64F
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Min.
—
DC CHARACTERISTICS
Param.
No.
Sym.
—
D1
D2
D3
V
IH
V
IL
V
HYS
Characteristic
A0, A1, A2, WP, SCL
and SDA pins
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs (SDA,
SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Typ.
—
—
—
—
Max.
—
—
0.3 V
CC
0.2 V
CC
—
Units
—
V
V
V
V
—
—
Conditions
0.7 V
CC
—
0.05 V
CC
V
CC
2.5V
V
CC
2.5V
V
CC
2.5V
(Note 1)
D4
D5
D6
D7
D8
D9
D10
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
read
I
CCS
—
—
—
—
—
—
—
—
—
—
—
—
0.1
0.05
.01
—
0.40
±1
±1
10
3
400
1
5
V
A
A
pF
mA
A
A
A
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
Industrial
Automotive
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
I
CC
write
Operating current
Standby current
Note 1:
2:
This parameter is periodically sampled and not 100% tested.
Typical measurements taken at room temperature.
DS22154B-page 2
2009-2012 Microchip Technology Inc.
24AA64F/24LC64F/24FC64F
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): V
CC
= +2.5V to 5.5V T
A
= -40°C to 125°C
Characteristic
Clock frequency
Min.
—
—
—
—
4000
600
600
500
4700
1300
1300
500
—
—
—
—
—
4000
600
600
250
4700
600
600
250
0
250
100
100
4000
600
600
250
4000
600
600
4700
1300
1300
Max.
100
400
400
1000
—
—
—
—
—
—
—
—
1000
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
kHz
Conditions
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC64F
All except, 24FC64F
1.7V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
(Note
2)
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC64F
1.7 V
V
CC
2.5V
2.5 V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5 V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC64F
AC CHARACTERISTICS
Param.
No.
1
Sym.
F
CLK
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note
1)
SDA and SCL fall time
(Note
1)
ns
5
6
T
F
ns
ns
T
HD
:
STA
Start condition hold time
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
2009-2012 Microchip Technology Inc.
DS22154B-page 3
24AA64F/24LC64F/24FC64F
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): V
CC
= +2.5V to 5.5V T
A
= -40°C to 125°C
Characteristic
Output valid from clock
(Note
2)
Min.
—
—
—
—
4700
1300
1300
500
10 + 0.1C
B
Max.
3500
900
900
400
—
—
—
—
250
250
50
5
—
Units
ns
Conditions
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC64F
2.5V
V
CC
5.5V 24FC64F
All except, 24FC64F
(Note
1)
24FC64F
(Note
1)
All except, 24FC64F
(Notes
1
and
3)
—
AC CHARACTERISTICS
Param.
No.
13
Sym.
T
AA
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
C
B
100 pF
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or
page)
Endurance
ns
15
T
OF
ns
16
17
18
T
SP
T
WC
—
—
—
1,000,000
ns
ms
cycles Page Mode 25°C, 5.5V
(Note
4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
FIGURE 1-3:
BUS TIMING DATA
5
2
D3
4
SCL
SDA
IN
7
6
16
3
8
9
10
13
SDA
OUT
(protected)
(unprotected)
14
WP
11
12
DS22154B-page 4
2009-2012 Microchip Technology Inc.
24AA64F/24LC64F/24FC64F
2.0
PIN DESCRIPTIONS
PIN FUNCTION TABLE
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
TDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
SOT-23
—
—
—
2
3
1
5
4
Description
Chip Address Input
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7V to 5.5V Power Supply
The descriptions of the pins are listed in
Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
V
SS
SDA
SCL
WP
V
CC
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX64F for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
CC
or V
SS
.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 package.
The SCL input is used to synchronize the data transfer
from and to the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited for upper 1/4 of the array
(1800h-1FFFh), but read operations are not affected.
3.0
FUNCTIONAL DESCRIPTION
2.2
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to V
CC
(typical 10 k for 100 kHz, 2 kfor 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24XX64F supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX64F works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
2009-2012 Microchip Technology Inc.
DS22154B-page 5
