To our customers,
Old Company Name in Catalogs and Other Documents
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas
Electronics Corporation
took over all the business of both
companies.
Therefore, although the old company name remains in this document, it is a valid
Renesas
Electronics document. We appreciate your understanding.
Renesas Electronics website:
http://www.renesas.com
April 1
st
, 2010
Renesas Electronics Corporation
Issued by:
Renesas Electronics Corporation
(http://www.renesas.com)
Send any inquiries to
http://www.renesas.com/inquiry.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is
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“Standard”:
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
2SJ517
Silicon P Channel MOS FET
REJ03G0874-0400
(Previous: ADE-208-575B)
Rev.4.00
Sep 07, 2005
Description
High speed power switching
Features
•
Low on-resistance
R
DS (on)
= 0.18
Ω
typ. (at V
GS
= –4 V, I
D
= –1 A)
•
Low drive current
•
High speed switching
•
2.5 V gate drive devices.
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK
R
)
D
3
2
1
G
4
1. Gate
2. Drain
3. Source
4. Drain
S
Note: Marking is “YY”.
*UPAK is a trademark of Renesas Technology Corp.
Rev.4.00 Sep 07, 2005 page 1 of 6
2SJ517
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body to drain diode reverse drain current
Channel dissipation
Channel temperature
Symbol
V
DSS
V
GSS
I
D
I
D (pulse)
I
DR
Note 1
Value
–20
±10
–2
–4
–2
1
150
–55 to +150
Unit
V
V
A
A
A
W
°C
°C
Pch
Tch
Note 2
Storage temperature
Tstg
Notes: 1. PW
≤
100
µs,
duty cycle
≤
10%
2. When using the aluminium ceramic board (12.5
×
20
×
0.7 mm)
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Static drain to source on state resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body to drain diode forward voltage
Body to drain diode reverse recovery
time
Note:
3. Pulse test
Symbol
V
(BR) DSS
V
(BR) GSS
I
DSS
I
GSS
V
GS (off)
R
DS (on)
R
DS (on)
|y
fs
|
Ciss
Coss
Crss
t
d (on)
t
r
t
d (off)
t
f
V
DF
t
rr
Min
–20
±10
—
—
–0.5
—
—
1.8
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
0.18
0.27
3.0
320
190
90
14
75
90
90
–0.95
70
Max
—
—
–10
±10
–1.5
0.24
0.43
—
—
—
—
—
—
—
—
—
—
Unit
V
V
µA
µA
V
Ω
Ω
S
pF
pF
pF
ns
ns
ns
ns
V
ns
Test Conditions
I
D
= –10 mA, V
GS
= 0
I
G
=
±100 µA,
V
DS
= 0
V
DS
= –20 V, V
GS
= 0
V
GS
=
±8
V, V
DS
= 0
I
D
= –1 mA, V
DS
= –10 V
I
D
= –1 A, V
GS
= –4 V
Note 3
I
D
= –1 A, V
GS
= –2.5 V
I
D
= –1 A, V
DS
= –10 V
V
DS
= –10 V
V
GS
= 0
f = 1 MHz
V
GS
= –4 V
I
D
= –1 A
R
L
= 10
Ω
I
F
= –2 A, V
GS
= 0
I
F
= –2 A, V
GS
= 0
di
F
/dt = 50 A/µs
Note 3
Note 3
Rev.4.00 Sep 07, 2005 page 2 of 6
2SJ517
Main Characteristics
Power vs. Temperature Derating
2.0
Maximum Safe Operation Area
–10
10
Pch (W)
I
D
(A)
Test Condition:
When using the aluminum ceramic
board (12.5
×
20
×
70 mm)
–3
–1
1.5
PW
µ
s
10
=
10
1
m
s
m
0
s
µ
s
Channel Dissipation
Drain Current
D
C
–0.3
1.0
O
(1
pe
sh
ra
t
ot
)
0.5
–0.1 Operation in
this area is
limited by R
DS (on)
–0.03
Ta = 25°C
–0.01
–1
–0.1 –0.3
io
n
0
0
50
100
150
200
–3
–10
–30
–100
Ambient Temperature
Ta (°C)
Drain to Source Voltage V
DS
(V)
Typical Output Characteristics
–5
–10 V
–5
Pulse Test
–2.5 V
–4 V
–3 V
Typical Transfer Characteristics
V
DS
= –10 V
Pulse Test
I
D
(A)
I
D
(A)
–4
–4
–25°C
–3
25°C
Tc = 75°C
–3
Drain Current
–2
–2 V
Drain Current
–10
–2
–1
V
GS
= –1.5 V
0
0
–2
–4
–6
–8
–1
0
0
–1
–2
–3
–4
–5
Drain to Source Voltage
V
DS
(V)
Gate to Source Voltage
V
GS
(V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source on State Resistance
R
DS (on)
(Ω)
Drain to Source Saturation Voltage
V
DS (on)
(V)
–1.0
Pulse Test
Static Drain to Source on State Resistance
vs. Drain Current
1
0.5
V
GS
= –2.5 V
0.2
0.1
0.05
–4 V
–0.8
–0.6
–0.4
I
D
= –2 A
–0.2
–1 A
–0.5 A
0
0
–2
–4
–6
–8
–10
0.02
Pulse Test
0.01
–0.1 –0.2 –0.5
–1
–2
–5
–10
Gate to Source Voltage
V
GS
(V)
Drain Current
I
D
(A)
Rev.4.00 Sep 07, 2005 page 3 of 6
