Product Specification
PE3503
Product Description
The PE3503 is a high performance monolithic UltraCMOS™
prescaler with a fixed divide ratio of 8. Its operating frequency
range is 1500 MHz to 3500 MHz. The PE3503 operates on a
nominal 3 V supply and draws only 12 mA. It is packaged in a
small 8-lead MSOP and is ideal for microwave PLL synthesis
solutions.
The PE3503 is manufactured in Peregrine’s patented Ultra
Thin Silicon (UTSi©) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
3500 MHz Low Power UltraCMOS™
Divide-by-8 Prescaler
Features
•
High-frequency operation: 1500 MHz
to 3500 MHz
•
Fixed divide ratio of 8
•
Low-power operation: 12 mA typical
@ 3 V across frequency
•
Small package: 8-lead MSOP
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
8-lead MSOP
D
IN
Pre-Amp
Q
D
Q
D
Q
OUT
Output
Buffer
CLK QB
CLK QB
CLK QB
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
Ω
)
V
DD
= 3.0 V, -40° C
≤
T
A
≤
85° C, unless otherwise specified
Parameter
Supply Voltage
Supply Current
Frequency Range (F
IN
)
Input Power (P
IN
)
Conditions
Minimum
2.85
Typical
3.0
12
Maximum
3.15
17
3500
+5
+5
Units
V
mA
MHz
dBm
dBm
dBm
1500
1500 MHz
≤
F
in
≤
3200 MHz
3200 MHz < F
in
≤
3500 MHz
-10
0
-5
Output Power
Document No. 70-0050-04
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
PE3503
Product Specification
Figure 3. Pin Configuration (Top View)
1
2
8
7
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
V
DD
GND
IN
OUT
3503
DEC
3
4
6
5
GND
GND
GND
Table 2. Pin Descriptions
Pin
No.
1
2
Pin
Name
V
DD
IN
Device Functional Considerations
Description
Power supply pin. Bypassing is required.
Input signal pin. Should be coupled with a
capacitor (eg 15 pF)
Power supply decoupling pin. Place a
capacitor as close as possible and connect
directly to the ground plane (eg 10 nF and
10 pF).
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Ground pin.
Ground pin.
Divided frequency output pin. This pin
should be coupled with a capacitor (eg 100
pF).
Ground pin.
3
DEC
4
5
6
7
8
GND
GND
GND
OUT
GND
The PE3503 takes an input signal frequency from
1500 MHz to 3500 MHz and produces an output
signal frequency one-eighth that of the supplied
input. In order for the prescaler to work properly,
several conditions need to be adhered to. It is
crucial that pin 3 be supplied with a bypass
capacitor to ground. In addition, the input and
output signals (pins 2 & 7, respectively) need to
be AC coupled via an external capacitor as shown
in the test circuit in Figure 7.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance.
Table 3. Absolute Maximum Ratings
Symbol
V
DD
T
ST
T
OP
V
ESD
P
INMAX
Parameter/Conditions
Supply voltage
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model)
Maximum input power
Min
Max
4.0
Units
V
°C
°C
V
-65
-40
250
150
85
10
dBm
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0050-04
│
UltraCMOS™ RFIC Solutions
PE3503
Product Specification
Typical Performance Data
Figure 4. Input Sensitivity
Figure 5. Device Current
0
-5
Sensitivity (dBm)
25C
-40C
85C
15
14
Current (mA)
13
12
11
10
9
8
25C
-40C
85C
-10
-15
-20
-25
-30
0.5
1.5
2.5
Frequency (GHz)
3.5
4.5
0.5
1.5
2.5
Frequency (GHz)
3.5
4.5
Figure 6. Output Power
3.0
2.5
Power (dBm)
2.0
1.5
1.0
0.5
0.0
-0.5
0.5
1.5
25C
-40C
85C
2.5
Frequency (GHz)
3.5
4.5
Document No. 70-0050-04
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Page 3 of 7
PE3503
Product Specification
Figure 7. Test Circuit Block Diagram
VDD
3 V +/- 0.15 V
+
-
10 pF
1000 pF
1
8
7
100 pF
50 Ω
50 Ω
15 pF
2
PE3503
3
Signal Generator
4
5
6
Spectrum
Analyzer
10 nF
10 pF
Figure 8. High Frequency System Application
The wideband frequency of operation of the PE3503 makes it an ideal part for use in a
DBS downconverter system.
INPUT FROM
DBS 1
ST
IF
BPF
SAW
AGC
FM
DEMOD
BASEBAND
OUTPUT
DIVIDE-BY-8
PE3291
PE3503
LOW NOISE
PLL SYNTH
LPF
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 7
Document No. 70-0050-04
│
UltraCMOS™ RFIC Solutions
PE3503
Product Specification
Evaluation Kit
Evaluation Kit Operation
The MSOP Prescaler Evaluation Board was designed
to help customers evaluate the
PE3503
Divide-by-8
Prescaler. On this board, the device input (pin 2) is
connected to connector J1 through a 50
Ω
transmission
line. A series capacitor (C3) provides the necessary
DC block for the device input. It is important to note
that the value of this capacitance will impact the
performance of the device. A value of 15 pF was found
to be optimal for this board layout; other applications
may require a different value.
The device output (pin 7) is connected to connector J3
through a 50
Ω
transmission line. A series capacitor
(C1) provides the necessary DC block for the device
output. Note that this capacitor must be chosen to
have a low impedance at the desired output frequency
the device. The value of 100 pF was chosen to provide
a wide operating range for the evaluation board.
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane model with trace width
of 0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and
ε
r
of 4.4. Note
that the predominate mode for these transmission lines
is coplanar waveguide. J2 provides DC power to the
device. Starting from the lower left pin, the second pin
to the right (J2-3) is connected to the device V
DD
pin
(1). Two decoupling capacitors (10 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
The DEC pin (3) must be connected to a low
impedance AC ground for proper device operation. On
the board, two decoupling capacitors (C6 = 10 nF, C4 =
10 pF), located on the back of the board, perform this
function.
Applications Support
If you have a problem with your evaluation kit or if you
have applications questions call (858) 731-9400 and
ask for applications support. You may also contact us
by fax or e-mail:
Fax:
(858) 731-9499
E-Mail:
help@psemi.com
Figure 9. Evaluation Board Layouts
Peregrine Specification 101/0035
Figure 10. Evaluation Board Schematic
Peregrine Specification 102/0055
Document No. 70-0050-04
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 7
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