THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
MA9000 Series
MAY 1995
DS3598-3.4
MA9000 Series
SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS
The logic building block for the GPS double level metal
CMOS/SOS gate arrays is a four transistor ‘cell-unit’
equivalent in size to a 2 input NAND gate. Back to back cell-
units as illustrated, organised in rows, form the core of the
array
The interconnection patterns that cause groups of cell units
within a row, to become defined logic cells, and the models
which are used to simulate these cells, are stored as software
in LIBRARIES. Cells up to the complexity of, say, multiple bit
shift registers are treated in this way.
Higher complexity functions are described by MACROS as
the interconnection of defined cells. Macros are ‘hard’, ‘soft’, or
‘firm’ according to the constraints that are applied to the
distribution of the component cells within the array and
whether the full function is simulated by a model or by the
additive effects of the component cells.
FEATURES
s
s
s
s
s
Radiation Hard to 1MRad(Si)
High SEU Immunity, Latch-Up Free
Double-Level-Metal CMOS/SOS Technology
2.5 Micron Design Rules
Typical Gate Delay 1.2nS With 2 Loads, 60MHz Toggle
Speeds
s
Comprehensive Library of Logic Cells and Logic Function
Building Macros
s
100% Automatic Place and Route for Typically 70%
Utilisation
Figure 1: Cell Unit
ARRAY OPTIONS
Array
Type
MA9007
MA9024
MA9040
Cell
Units
748
2484
4048
I/O
46
80
102
Bonding Pads
Power
Total
2
4
4
48
84
106
Each cell-unit is equivalent to a 2 input NAND gate.
Any l/O site may be configured as a power pad to give
flexible bonding options, but to standardise testing, preferred
positions exist.
1
MA9000 Series
CHARACTERISITICS & RATINGS
Symbol
V
DD
V
I
T
A
T
S
Parameter
Supply voltage
Input voltage
Operating temperature
Storage temperature
Min.
-0.5
-0.3
-55
-65
Max.
7
V
DD
+ 0.3
125
150
Units
V
V
˚C
˚C
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions,
or at any other condition above those indicated in the
operations section of this specification. is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 1: Absolute Maximum Ratings
Symbol
V
DD
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
I
L
I
OZ
I
DD
Parameter
Supply voltage
TTL input high voltage
TTL input low voltage
CMOS input high voltage
CMOS input low voltage
TTL output high voltage
TTL output low voltage
CMOS output high voltage
CMOS output low voltage
Input leakage current
Output leakage current
Power supply current
Conditions
-
-
-
-
-
I
OH
= -2mA
I
OL
= 5mA
I
OH
= -4mA
I
OL
= 4mA
-
Tristate Output
-
Min.
4.5
2.0
-
80
-
2.4
-
90
-
-
-
-
Typ.
5.0
-
-
-
-
-
-
-
-
-
-
0.1
Max.
5.5
-
0.8
-
20
-
0.4
-
10
10
30
*
Units
V
V
V
%V
DD
%V
DD
V
V
%V
DD
%V
DD
µA
µA
mA
V
DD
= 5V
±10%,
over full operating temperature.
* Dependent on array type.
Table 2: Electrical Characteristics
AC CHARACTERISTICS
Cell Name
NOP
NOR2
Function
Push/Pull Output Buffer
2 Input NOR
O/P Edge
Rising
Falling
Rising
Falling
Rising CK - QB
Falling CK - QB
Data Set-up time
Data Hold time
Inherent Delay
0.5
0.3
1.6
0.8
4.6
7.8
7.1
4.4
Per 1pF Load*
0.4
0.2
13.6
5.0
13.7
13.6
-
-
Units
ns
ns
RDT
Reset D Type
ns
* 1pF is equivalent to fanout of 5 standard gates
Table 3: Electrical Characteristics
2
MA9000 Series
PROPAGATION DELAY
Worst case maximum propagation delays for 5 volts
working and 25°C are stated in the cell libraries. These are for
the data change or state change which gives the greatest
delay. Typical process figures under the same conditions are
generally 60% of those listed.
Use the following normalised graphs to obtain converstion
factors to predict delays at any other working temperature or
voltage:
PACKAGE OPTIONS
MA9007
196 x 129
DIL14
DIL16
DIL20
DIL24
DIL28
DIL40
DIL48
DIL64
LCC28
LCC40
LCC44
LCC48
LCC68
LCC84
FPK16
FPK20
FPK24
FPK28
FPK64
FPK68
FPK84
PGA68
PGA84
PGA120
PGA144
DIL = Dual in line
LCC = Leadless chip carrier
FPK = Leaded flatpack
PGA = Pin grid array
These are standard packages. If your package
requirement is not shown above, discuss other
options with an applications engineer.
X
X
X
X
X
X
MA9024
247 x 240
MA9040
301 x 302
Propagation Delay Factor
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Figure 2: Propogation Delay vs Temperature & Propogation
Delay vs Supply Voltage
Propagation Delay Factor
3
MA9000 Series
RADIATION TOLERANCE
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
GPS can provide radiation testing compliant with MIL-STD-
883C remote sensing method 1019 notice 5.
Total Dose (Function to specification)*
Transient Upset (Stored data loss)
Transient Upset (Survivability)
Neutron Hardness (Function to specification)
Single Event Upset**
Latch Up
3x10
5
Rad(Si)
5x10
10
Rad(Si)/sec
>1x10
12
Rad(Si)/sec
>1x10
15
n/cm
2
<1x10
-10
Errors/bit day
Not possible
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Table 4: Radiation Hardness Parameters
CELL LIBRARY QUICK GUIDE
Cell Name
Function
Cell Units
Cell Name
NOR12
NOR16
OR2
OR3
OR4
ANDNOR
ANDOR
ORNAND
ORAND
A2N01
A201
02NA1
02A1
EXNOR
EXORN
SEL21NV
SEL2
SEL41NV
SEL4
Function
12 input NOR
16 input NOR
2 input OR
3 input OR
4 Input OR
2 + 2 input AND/NOR
2 + 2 input AND/OR
2 + 2 OR/NAND
2 + 2 OR/AND
2 + 1 Input AND/NOR
2 + 1 input AND/OR
2 + 1 input OR/NAND
2 + 1 input OR/AND
Exclusive NOR
Exclusive OR
Select 1 of 2 (inverting)
Select 1 of 2
4 bit data selector (inverting)
4 bit data selector
Cell Units
8
11
2
2
3
2
3
2
3
2
2
2
2
3
3
3
3
6
7
COMBINATIONAL GATES
INV
DUALINV
INVB
INVC
BUFF
BUFFB
BUFFC
NAND2
NAND2B
NAND3
NAND4
NAND8
NAND12
NAND16
AND2
AND3
AND4
NOR2
NOR2B
NOR3
NOR4
NOR8
Inverter
Dual inverter
Fast inverter
Super fast inverter
Non-inverting buffer
Fast non-inverting buffer
Super fast non-inverting buffer
2 input NAND
Fast 2 input NAND
3 input NAND
4 input NAND
8 input NAND
12 input NAND
16 input NAND
2 input AND
3 input AND
4 input AND
2 input NOR
Fast 2 input NOR
3 input NOR
4 input NOR
8 input NOR
1
1
1
2
1
2
3
1
2
2
2
6
8
11
2
2
3
1
2
2
2
6
4
FPGA/CPLD
