Preliminary Specification
PE42660 DIE
Product Description
The PE42660 is a HaRP™-enhanced SP6T RF Switch
developed on the UltraCMOS™ process technology. It
addresses the specific design needs of the Quad-Band GSM
Handset Antenna Switch Module Market. On-chip CMOS
decode logic facilitates three-pin low voltage CMOS control,
while high ESD tolerance of 1500 V at all ports, no blocking
capacitor requirements, and on-chip SAW filter over-voltage
protection devices make this the ultimate in integration and
ruggedness.
Peregrine’s HaRP™ technology enhancements deliver high
linearity and exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™ process, providing
performance superior to GaAs with the economy and
integration of conventional CMOS.
SP6T UltraCMOS™ 2.75 V Switch
100 – 3000 MHz
Features
•
Three pin CMOS logic control with
integral decoder/driver
•
Exceptional harmonics performance:
2f
o
= -88 dBc and 3f
o
= -85 dBc
•
Low TX insertion loss: 0.55 dB at
900 MHz, 0.65 dB at 1900 MHz
•
TX – RX Isolation of 48 dB at 900 MHz,
40 dB at 1900 MHz
•
1500 V HBM ESD tolerance all ports
•
41 dBm P1dB
•
No blocking capacitors required
Figure 1. Functional Diagram
Figure 2. Die Top View
TX1
TX1
RX1
ANT
RX1
GND
RX2
TX2
RX2
GND
GND
GND
RX3
GND
RX3
TX2
RX4
GND
CMOS
Control/Driver
and ESD
RX4
GND
GND
V
DD
V3
GND
V2 V1
GND
V1
V2
V3
Document No. 70-0192-02
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
PE42660
Preliminary Specification
Table 1. Electrical Specifications @ +25 °C, V
DD
= 2.75 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operational Frequency
ANT - TX - 850 / 900 MHz
ANT - TX - 1800 / 1900 MHz
ANT - RX - 850 / 900 MHz
ANT - RX - 1800 / 1900 MHz
TX - RX - 850 / 900 MHz
TX - RX - 1800 / 1900 MHz
TX - TX - 850 / 900 MHz
TX - TX - 1800 / 1900 MHz
ANT - TX - 850 / 900 MHz
ANT - TX - 1800 / 1900 MHz
850 / 900 MHz
1800 / 1900 MHz
35 dBm TX Input - 850 / 900 MHz
33 dBm TX Input - 1800 / 1900 MHz
35 dBm TX Input - 850 / 900 MHz
33 dBm TX Input - 1800 / 1900 MHz
(10-90%) (90-10%) RF
Conditions
Typical
100-3000
0.55
0.65
0.90
1.00
48
40
29
25
31
25
22
23
-88
-85
-85
-84
2
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Insertion Loss
Isolation
Return Loss
dB
2nd Harmonic
dBc
3rd Harmonic
Switching Time
dBc
µs
Table 2. Operating Ranges
Parameter
Temperature range
V
DD
Supply Voltage
I
DD
Power Supply Current
(V
DD
= 2.75 V)
TX input power
1
(VSWR
≤
3:1)
RX input power
1
(VSWR
≤1:1)
Control Voltage High
Control Voltage Low
Symbol Min Typ Max Units
T
OP
V
DD
I
DD
-40
2.65 2.75
13
+85
2.85
20
°C
V
µA
P
IN
P
IN
V
IH
V
IL
0.7 x
V
DD
+35
+20
dBm
dBm
V
0.3 x
V
DD
V
Note: 1. Assumes RF input period of 4620
µs
and duty cycle of 50%.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
Document No. 70-0192-02
│
UltraCMOS™ RFIC Solutions
PE42660
Preliminary Specification
Figure 3. Pin Configuration (Top View)
ANT
TX1
2
1
20
19
Table 4. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
TX input power (50
Ω)
4,5
RX input power (50
Ω)
4,5
TX input power (VSWR
∞
:1)
4,5
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+ 0.3
+150
+38
Units
V
V
°C
dBm
RX1
GND
RX2
GND
RX3
GND
RX4
GND
V
DD
V
I
T
ST
P
IN
(50
Ω)
P
IN
(
∞
:1)
GND
GND
3
18
17
TX2
GND
4
5
PE42660
Die
16
15
14
13
+23
+35
1500
dBm
V
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
6
7
8
9
10
11
12
V
ESD
ESD Voltage at ANT Port
(IEC 61000-4-2)
1700
V
V
DD
V3
V2
GND
GND
V1
GND
Table 3. Pin Descriptions
Pin No.
1
3
2
3
3
2
4
3
5
2
6
2
7
8
9
2
10
11
12
2
13
2
14
3
15
2
Notes: 4. Assumes RF input period of 4620
µ
s and duty cycle of 50%.
5. V
DD
within operating range specified in Table 2.
Description
Pin Name
ANT
TX1
GND
TX2
GND
GND
V
DD
V3
GND
V2
V1
GND
GND
RX4
GND
RX3
GND
RX2
GND
RX1
RF Common – Antenna
RF I/O - TX1
Ground (Requires two bond wires)
RF I/O – TX2
Ground
Ground
Supply
Switch control input, CMOS logic level
Ground
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Ground
Ground
RF I/O – RX4
Ground
RF I/O – RX3
Ground
RF I/O – RX2
Ground
RF I/O – RX1
Part performance is not guaranteed under these
conditions. Exposure to absolute maximum
conditions for extended periods of time may
adversely affect reliability. Stresses in excess of
absolute maximum ratings may cause permanent
damage.
Table 5. Truth Table
Path
ANT – RX1
ANT – RX2
ANT – RX3
ANT – RX4
ANT - TX1
ANT - TX2
V3
0
0
0
0
1
1
V2
0
0
1
1
0
1
V1
0
1
0
1
x
x
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
16
3
17
2
18
3
19
2
20
3
Notes: 2. Bond wires should be physically short and connected to
ground plane for best performance.
3. Blocking capacitors needed only when non-zero DC
voltage present.
Document No. 70-0192-02
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
PE42660
Preliminary Specification
Evaluation Kit
The SP6T Evaluation Kit board was designed to
ease customer evaluation of the PE42660 RF
switch.
The PE42660 has two high power TX ports and four
high isolation RX ports. The TX ports are symmetric
and are designed as paths for the 850, 900, 1800, or
1900 MHz bands. The RX ports are also symmetric
and can be assigned to any of these frequency
bands.
The ANT port connects through a 50
Ω
transmission
line to the top SMA connector, J1. The RX and TX
ports connect through 50
Ω
transmission lines to
SMA connectors J2 – J7. A through 50
Ω
transmission line between SMA connectors J9 and
J10 allows estimation of the PCB losses over
environmental conditions. An open transmission line
connected to J11 is also provided.
J8 supplies DC power to the pin marked V
DD
and the
bottom row of pins, which is GND. 1 MΩ pull-up
resistors are connected from V
DD
to each of the three
control logic inputs: V1, V2, and V3. These pull-up
resistors are provided for ease of evaluation on this
board and are not required for the PE42660 to
operate.
Adding a jumper between a control pin and the
adjacent GND pin on the bottom row of J8 will set a
logic-0 on that control pin. Removing the jumper will
set a logic-1. To evaluate the PE42660, add or
remove jumpers according to the truth table in
Table 5.
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0205
ANT
RX1
TX1
TX2
RX2
RX3
RX4
Through-Line
Open Line
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0267
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 9
Document No. 70-0192-02
│
UltraCMOS™ RFIC Solutions
PE42660
Preliminary Specification
Electrical Test and Performance Specifications
PE42660 dice are 100% electrically tested for the
parameters listed below from Table 1 and Table 2. All
other parameters are guaranteed through design and
characterization.
•
•
•
•
•
Insertion Loss (all ports)
TX1 & TX2 Harmonics
TX – RX Isolation
I
DD
supply current
Control pin leakages
Figure 6. Wafer on Film Frame
Wafer and Die Packaging
Peregrine Semiconductor has two methods for shipping
dice to our customers. The shipping option used is
based on the customer’s requirements and the number
of dice.
Peregrine offers product dice in two packaging options:
Standard Die Carrier Packages (waffle pack) and dice
on Film Frames.
Figure 7. Dice and Wafer Processing Flow
Wafer
Processing
Visual
Inspection
100%
Electrical Test
Wafer
Singulation
Dice Picking
Process Control
Monitor (PCM)
Wafer Level
Reliability (WLR)
Ink Reject Die or
Electronic Wafer
Map
100% Visual
Inspection
Carrier Loading
Wafer Mount/Dicing
In preparation for dicing, wafers are thinned and
polished and 100% electrically probed prior to
mounting on film frame tape and rings. Figure 6 shows
a wafer mounted on film frame using PVC backed
mounting tape. In preparation for shipment, wafers are
visually inspected after singulation and shipped with an
electronic map file providing good dice locations.
Backgrind
and Polish
Outgoing QA
Inspection
Pack and Ship
Wafers
Pack and Ship
Dice
Figure 8. Waffle Pack
Storage and Preservation
Proper storage conditions are necessary to prevent
product contamination and/or degradation after
shipment.
Product should be stored in the original unopened
packaging or, once opened, in a nitrogen purged
cabinet at room temperature (45% + 15% relative
humidity controlled environment).
Singulated wafers mounted on film frames are intended
for immediate use and have a limited shelf life. This is
primarily due to the nature of the adhesive tape used
for mounting the product. This product can be stored
up to 30 days. This applies whether or not the material
has remained in its original sealed container. To reduce
the risk of contamination or degradation, it is
recommended that product not being used in the
assembly process be returned to their original
containers and resealed with a vacuum seal process.
Document No. 70-0192-02
│
www.psemi.com
Standard Die Carrier Package/Waffle Pack
Waffle packs are available to customers during product
development and prototyping phase only. Orders will
move to film frames at production launch or for large
quantity requirements.
Dice have been 100% electrically probed, singulated,
visually inspected and are packaged in a 2”x2” waffle
pack (400 dice per waffle pack).
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
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