Si516
D
U A L
F
REQUENCY
V
OLTAGE
- C
ON TROLLED
C
R YS TA L
O
SCILLATOR
( V C X O ) 1 0 0 k H
Z T O
250 M H
Z
Features
Supports any frequency from
100 kHz to 250 MHz
Two selectable output frequencies
Low-jitter operation
Short lead times: <2 weeks
AT-cut fundamental mode crystal
ensures high reliability/low aging
High power supply noise rejection
1% control voltage linearity
Available CMOS, LVPECL,
LVDS, and HCSL outputs
Optional 1:2 CMOS fanout buffer
3.3 and 2.5 V supply options
Industry-standard 5x7, 3.2x5, and
2.5x3.2 mm packages
Pb-free/RoHS-compliant
Selectable Kv (60, 90, 120,
150 ppm/V)
Si5602
5
X
7
MM
, 3.2
X
5
MM
2.5
X
3.2
MM
Ordering Information:
See page 14.
Pin Assignments:
See page 12.
Applications
SONET/SDH/OTN
PON
Low Jitter PLLs
xDSL
Broadcast video
Telecom
Switches/routers
FPGA/ASIC clock generation
Description
The Si516 dual frequency VCXO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional VCXO where a different crystal is required for each output
frequency, the Si516 uses one fixed crystal and Silicon Labs’ proprietary
synthesizer to generate any frequency across this range. This IC-based
approach allows the crystal resonator to provide enhanced reliability,
improved mechanical robustness, and excellent stability. In addition, this
solution provides superior control voltage linearity and supply noise
rejection, improving PLL stability and simplifying low jitter PLL design in
noisy environments. The Si516 is factory-configurable for a wide variety of
user specifications, including frequency, supply voltage, output format,
tuning slope and stability. Specific configurations are factory-programmed at
time of shipment, eliminating long lead times and non-recurring engineering
charges associated with custom frequency oscillators.
Vc 1
FS
GND
2
3
6 V
DD
5 NC
4 CLK
CMOS Dual VCXO
Vc
FS
G ND
1
2
3
6 V
DD
5 CLK–
4 CLK+
LVPECL/LVDS/HCSL/Dual CM OS
Dual VCXO
Functional Block Diagram
Rev. 1.1 12/17
Copyright © 2017 by Silicon Laboratories
Si516
Si516
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
11.1. Si516 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2
Rev. 1.1
Si516
1. Electrical Specifications
Table 1. Recommended Operating Conditions
V
DD
= 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Supply Voltage
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
Min
2.97
2.25
—
—
—
—
—
0.80 x V
DD
—
—
–40
Typ
3.3
2.5
24
22
42
44
—
—
—
45
—
Max
3.63
2.75
29
26
46
47
22
—
0.20 x V
DD
—
85
Unit
V
V
mA
mA
mA
mA
mA
V
V
k
o
C
Supply Current
I
DD
CMOS, 100 kHz,
single-ended
LVDS
(output enabled)
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
FS "1" Setting
FS "0" Setting
FS Internal Pull-Up Resistor
Operating Temperature
V
IH
V
IL
R
I
T
A
Rev. 1.1
3
Si516
Table 2. Vc Control Voltage Input
Parameter
Control Voltage Range
Control Voltage Tuning Slope
(10 to 90% V
DD
)
Kv Variation
Control Voltage Linearity
Modulation Bandwidth
Vc Input Impedance
V
DD
= 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Symbol
V
C
Kv
Kv_var
L
VC
BW
Z
VC
Test Condition
Min
0.1 x V
DD
Typ
V
DD
/2
Max
0.9 x V
DD
Unit
V
ppm/V
Ordering option
—
BSL
–5
—
—
60, 90, 120, 150
—
±1
10
100
±10
+5
—
—
%
%
kHz
k
Table 3. Output Clock Frequency Characteristics
V
DD
= 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Nominal Frequency
Symbol
F
O
F
O
S
T
A
APR
T
SU
T
D
T
D
t
FRQ
Test Condition
CMOS, Dual CMOS
LVDS/LVPECL/HCSL
T
A
= –40 to +85
o
C
Frequency drift over 10-year life
Ordering option
Minimum V
DD
until output fre-
quency (F
O
) within specification
F
O
> 10 MHz
F
O
< 10 MHz
F
O
> 10 MHz
F
O
< 10 MHz
Min
0.1
0.1
–20
—
Typ
—
—
—
—
Max
212.5
250
+20
±8.5
Unit
MHz
MHz
ppm
ppm
ppm
ms
µs
µs
µs
µs
ms
Temperature Stability
Aging
Minimum Absolute Pull Range
Startup Time
Disable Time
±30, ±50,±80, ±100
—
—
—
—
—
—
—
—
—
—
—
—
10
5
40
20
60
10
Enable Time
Settling Time after FS Change
4
Rev. 1.1
Si516
Table 4. Output Clock Levels and Symmetry
V
DD
= 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
CMOS Output Logic High
CMOS Output Logic Low
CMOS Output Logic High
Drive
CMOS Output Logic Low
Drive
CMOS Output Rise/Fall Time
(20 to 80% V
DD
)
Symbol
V
OH
V
OL
I
OH
I
OL
T
R
/T
F
Test Condition
Min
0.85 x V
DD
—
Typ
—
—
—
—
—
—
0.8
0.6
—
Max
—
0.15 x V
DD
—
—
—
—
1.2
0.9
565
Unit
V
V
mA
mA
mA
mA
ns
ns
ps
3.3 V
2.5 V
3.3 V
2.5 V
0.1 to 125 MHz,
C
L
= 15 pF
0.1 to 212.5 MHz,
C
L
= no load
–8
–6
8
6
—
—
—
LVPECL/HCSL Output
Rise/Fall Time
(20 to 80% V
DD
)
LVDS Output Rise/Fall Time
(20 to 80% V
DD
)
LVPECL Output Common
Mode
LVPECL Output Swing
LVDS Output Common Mode
LVDS Output Swing
HCSL Output Common Mode
HCSL Output Swing
Duty Cycle
T
R
/T
F
T
R
/T
F
V
OC
V
O
V
OC
V
O
V
OC
V
O
DC
50
to V
DD
– 2 V,
single-ended
50
to V
DD
– 2 V,
single-ended
100
line-line,
V
DD
= 3.3/2.5 V
Single-ended 100
differential termination
50
to
ground
Single-ended
—
—
0.55
1.13
0.25
0.35
0.58
48
—
V
DD
–
1.4 V
0.8
1.23
0.38
0.38
0.73
50
800
—
0.90
1.33
0.42
0.42
0.85
52
ps
V
V
PPSE
V
V
PPSE
V
V
PPSE
%
Rev. 1.1
5
