FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
Integrated Device Technology, Inc.
IDT29FCT52AT/BT/CT/DT
IDT29FCT2052AT/BT/CT
IDT29FCT53AT/BT/CT
FEATURES:
• Common features:
– Low input and output leakage
≤1µA
(max.)
– CMOS power levels
– True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for 29FCT52/29FCT53T:
– A, B, C and D speed grades
– High drive outputs (-15mA I
OH
, 64mA I
OL
)
– Power off disable outputs permit “live insertion”
• Features for 29FCT2052T:
– A, B and C speed grades
– Resistor outputs (-15mA I
OH
, 12mA I
OL
Com.)
(-12mA I
OH
, 12mA I
OL
Mil.)
– Reduced system switching noise
DESCRIPTION:
The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/
CT are 8-bit registered transceivers built using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis-
ters store data flowing in both directions between two bidirec-
tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.
The IDT29FCT52AT/BT/CT/DT and IDT29FCT2052AT/BT/
CT are non-inverting options of the IDT29FCT53AT/BT/CT.
The IDT29FCT2052AT/BT/CT has balanced drive outputs
with current limiting resistors. This offers low ground bounce,
minimal undershoot and controlled output fall times-reducing
the need for external series terminating resistors. The
IDT29FCT2052T part is a plug-in replacement for
IDT29FCT52T part.
FUNCTIONAL BLOCK DIAGRAM
(1)
CPA
CEA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
D
0
CE CP Q
0
D
1
D
2
Q
1
Q
2
OEB
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
D
3
Q
3
A
D
4
Reg. Q
4
D
5
D
6
D
7
Q
5
Q
6
Q
7
Q
0
Q
1
Q
2
D
0
D
1
D
2
Q
3
D
3
B
Q
4
Reg. D
4
Q
5
Q
6
OEA
D
5
D
6
Q
7
CE CP D
7
NOTE:
1. IDT29FCT52T/IDT29FCT2052T function is shown. IDT29FCT53T is
the inverting option.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CPB
CEB
2629 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
JUNE 1995
DSC-4224/5
6.1
1
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OEB
CPA
CEA
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
P24-1
D24-1
SO24-2
SO24-7*
SO24-8*
&
E24-1
21
20
19
18
17
16
15
14
13
CPA
CEA
GND
NC
CEB
CPB
OEA
Vcc
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
2629 drw 02
B
4
B
3
B
2
NC
B
1
B
0
OEB
B
5
B
6
B
7
NC
Vcc
A
7
A
6
4
5
6
7
8
9
10
3
2
1
28 27 26
25
24
23
L28-1
22
21
20
11
19
12 13 14 15 16 17 18
A
5
A
4
A
3
NC
A
2
A
1
A
0
2629 drw 03
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
LCC
TOP VIEW
PIN DESCRIPTION
Name
A
0-7
B
0-7
CPA
I/O
I/O
I/O
I
I
I
I
I
I
Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
Clock for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition of
the CPA signal.
Clock Enable for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal. When
CEA
is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
Output Enable for the A Register. When
OEB
is LOW, the A Register outputs are enabled onto the B
0-7
lines. When
OEB
is HIGH, the B
0-7
outputs are in the high-impedance state.
CEA
OEB
CPB
Clock for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition of
the CPB signal.
Clock Enable for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal. When
CEB
is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
Output Enable for the B Register. When
OEA
is LOW, the B Register outputs are enabled onto the A
0-7
lines. When
OEA
is HIGH, the A
0-7
outputs are in the high-impedance state.
CEB
OEA
2629 tbl 01
6.1
2
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
REGISTER FUNCTION TABLE
(1)
(Applies to A or B Register)
D
X
L
H
Inputs
CP
X
↑
↑
OUTPUT CONTROL
(1)
Internal
Y-Outputs
52/2052
Z
L
H
53
Z
H
L
2629 tbl 03
CE
H
L
L
Internal
Q
NC
L
H
Function
Hold Data
Load Data
2629 tbl 02
OE
H
L
L
Q
X
L
H
Function
Disable Outputs
Enable Outputs
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2640 lnk 05
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°C
°C
°C
W
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2529 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.1
3
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
Unit
V
V
µA
µA
µA
V
mV
mA
2629 tbl 06
V
CC
= Max., V
IN
= GND or V
CC
OUTPUT DRIVE CHARACTERISTICS FOR 29FCT52T/29FCT53T
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –6mA MIL.
V
IN
= V
IH
or V
IL
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= Min.
I
OL
= 48mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 64mA COM'L.
(3)
V
CC
= Max., V
O
= GND
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2.0
—
–60
—
Typ.
(2)
3.3
3.0
0.3
–120
—
Max.
—
—
0.55
–225
±1
Unit
V
V
V
mA
µA
2629 tbl 07
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
OUTPUT DRIVE CHARACTERISTICS FOR 29FCT2052T
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OL
= 12mA
Min.
16
–16
2.4
—
Typ.
(2)
48
–48
3.3
0.3
Max.
—
—
—
0.50
Unit
mA
mA
V
V
2629 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
6.1
4
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
or
OE
B
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
A
or
OE
B
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
A
or
OE
B
= GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
V
IN
= V
CC
FCTxxxT
V
IN
= GND
FCT2xxxT
V
IN
= V
CC
FCTxxxT
V
IN
= GND
FCT2xxxT
V
IN
= 3.4V
FCTxxxT
—
—
—
—
0.06
1.5
0.6
2.0
1.1
0.12
3.5
2.2
5.5
4.2
mA
I
C
Total Power Supply Current
(6)
V
IN
= GND FCT2xxxT
V
IN
= V
CC
FCTxxxT
V
IN
= GND
FCT2xxxT
V
IN
= 3.4V
FCTxxxT
—
—
—
—
3.8
1.5
6.0
3.8
7.3
(5)
4.0
(5)
16.3
(5)
13.0
(
5)
V
IN
= GND FCT2xxxT
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2629 tbl 09
6.1
5
