54F 74F194 4-Bit Bidirectional Universal Shift Register
November 1994
54F 74F194
4-Bit Bidirectional Universal Shift Register
General Description
The ’F194 is a high-speed 4-bit bidirectional universal shift
register As a high-speed multifunctional sequential build-
ing block it is useful in a wide variety of applications It may
be used in serial-serial shift left shift right serial-parallel
parallel-serial and parallel-parallel data register transfers
The ’F194 is similar in operation to the ’F195 universal shift
register with added features of shift left without external
connections and hold (do nothing) modes of operation
Features
Y
Y
Y
Y
Typical shift frequency of 150 MHz
Asynchronous master reset
Hold (do nothing) mode
Fully synchronous serial or parallel data transfers
Commercial
74F194PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F194DM (Note 2)
74F194SC (Note 1)
74F194SJ (Note 1)
54F194FM (Note 2)
54F194LM (Note 2)
J16A
M16A
M16D
W16A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9498 – 1
TL F 9498 – 2
TL F 9498–5
TL F 9498–3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9498
RRD-B30M105 Printed in U S A
Unit Loading Fan Out
Pin
Names
S
0
S
1
P
0
– P
3
D
SR
D
SL
CP
MR
Q
0
– Q
3
54F 74F
Description
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
UL
HIGH LOW
10 10
10 10
10 10
10 10
10 10
10 10
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
b
1 mA 20 mA
Functional Description
The ’F194 contains four edge-triggered D flip-flops and the
necessary interstage logic to synchronously perform shift
right shift left parallel load and hold operations Signals
applied to the Select (S
0
S
1
) inputs determine the type of
operation as shown in the Mode Select Table Signals on
the Select Parallel data (P
0
– P
3
) and Serial data (D
SR
D
SL
)
inputs can change when the clock is in either state provid-
ed only that the recommended setup and hold times with
respect to the clock rising edge are observed A LOW sig-
nal on Master Reset (MR) overrides all other inputs and
forces the outputs LOW
Mode Select Table
Operating
Mode
Reset
Hold
Shift Left
Shift Right
Parallel Load
H (h)
e
High Voltage Level
L (l)
e
Low Voltage Level
p
n
(q
n
)
e
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition
X
e
Immaterial
Inputs
MR
L
H
H
H
H
H
H
S
1
X
l
h
h
l
l
h
S
0
X
l
l
l
h
h
h
D
SR
X
X
X
X
l
h
X
D
SL
X
X
l
h
X
X
X
P
n
X
X
X
X
X
X
p
n
Q
0
L
q
0
q
1
q
1
L
H
p
0
Outputs
Q
1
L
q
1
q
2
q
2
q
0
q
0
p
1
Q
2
L
q
2
q
3
q
3
q
1
q
1
p
2
Q
3
L
q
3
L
H
q
2
q
2
p
3
Logic Diagram
TL F 9498 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
65 C to
a
150 C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to V
CC
b
0 5V to
a
5 5V
twice the rated I
OL
(mA)
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
b
60
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
20 mA
I
OL
e
20 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V
V
OUT
e
0V
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
25
25
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 6
b
150
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
V
mA
mA
mA
V
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
33
46
3
AC Electrical Characteristics
74F
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PHL
Maximum Shift Frequency
Propagation Delay
CP to Q
n
Propagation Delay
MR to Q
n
105
35
35
45
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
150
52
55
86
70
70
12 0
Max
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
90
30
30
45
85
85
14 5
Max
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
90
35
35
45
80
80
14 0
Max
MHz
ns
ns
Units
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
rec
Setup Time HIGH or LOW
P
n
or D
SR
or D
SL
to CP
Hold Time HIGH or LOW
P
n
or D
SR
or D
SL
to CP
Setup Time HIGH or LOW
S
n
to CP
Hold Time HIGH or LOW
S
n
to CP
CP Pulse Width HIGH
MR Pulse Width LOW
Recovery Time MR to CP
40
40
10
0
10 0
80
0
0
50
50
90
Max
54F
T
A
V
CC
e
Mil
Min
60
40
15
10
10 5
80
0
0
55
50
90
Max
74F
T
A
V
CC
e
Com
Min
40
40
10
10
11 0
80
0
0
55
50
11 0
ns
ns
ns
Max
Units
ns
ns
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
194
S
C
X
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
X
e
Devices shipped in 13 reel
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
