54F 74F283 4-Bit Binary Full Adder with Fast Carry
November 1994
54F 74F283
4-Bit Binary Full Adder with Fast Carry
General Description
The ’F283 high-speed 4-bit binary full adder with internal
carry lookahead accepts two 4-bit binary words (A
0
–A
3
B
0
–B
3
) and a Carry input (C
0
) It generates the binary Sum
outputs (S
0
– S
3
) and the Carry output (C
4
) from the most
significant bit The ’F283 will operate with either active
HIGH or active LOW operands (positive or negative logic)
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial
74F283PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F283DM (Note 2)
74F283SC (Note 1)
74F283SJ (Note 1)
54F283FM (Note 2)
54F283LL (Note 2)
J16A
M16A
M16D
W16A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9513–1
IEEE IEC
TL F 9513 – 2
TL F 9513 – 3
TL F 9513–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9513
RRD-B30M105 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 20
10 20
10 10
50 33 3
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
1 2 mA
20
mA
b
1 2 mA
20
mA
b
0 6 mA
b
1 mA 20 mA
b
1 mA 20 mA
A
0
–A
3
B
0
–B
3
C
0
S
0
–S
3
C
4
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
Functional Description
The ’F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C
0
) The binary sum appears on the Sum
(S
0
– S
3
) and outgoing carry (C
4
) outputs The binary weight
of the various inputs and outputs is indicated by the sub-
script numbers representing powers of two
2
0
(A
0
a
B
0
a
C
0
)
a
2
1
(A
1
a
B
1
)
a
2
2
(A
2
a
B
2
)
a
2
3
(A
3
a
B
3
)
e
S
0
a
2S
1
a
4S
2
a
8S
3
a
16C
4
Where (
a
)
e
plus
Interchanging inputs of equal weight does not affect the op-
eration Thus C
0
A
0
B
0
can be arbitrarily assigned to pins
5 6 and 7 for DIPS and 7 8 and 9 for chip carrier packages
Due to the symmetry of the binary add function the ’F283
can be used either with all inputs and outputs active HIGH
(positive logic) or with all inputs and outputs active LOW
(negative logic) See
Figure 1
Note that if C
0
is not used it
must be tied LOW for active HIGH logic or tied HIGH for
active LOW logic
Due to pin limitations the intermediate carries of the ’F283
are not brought out for use as inputs or outputs However
other means can be used to effectively insert a carry into or
bring a carry out from an intermediate stage
Figure 2
shows how to make a 3-bit adder Tying the operand inputs
of the fourth adder (A
3
B
3
) LOW makes S
3
dependent only
on and equal to the carry from the third adder Using some-
what the same principle
Figure 3
shows a way of dividing
the ’F283 into a 2-bit and a 1-bit adder The third stage
adder (A
2
B
2
S
2
) is used merely as a means of getting a
carry (C
10
) signal into the fourth stage (via A
2
and B
2
) and
bringing out the carry from the second stage on S
2
Note
that as long as A
2
and B
2
are the same whether HIGH or
LOW they do not influence S
2
Similarly when A
2
and B
2
are the same the carry into the third stage does not influ-
ence the carry out of the third stage
Figure 4
shows a meth-
od of implementing a 5-input encoder where the inputs are
equally weighted The outputs S
0
S
1
and S
2
present a bina-
ry number equal to the number of inputs I
1
–I
5
that are true
Figure 5
shows one method of implementing a 5-input ma-
jority gate When three or more of the inputs I
1
–I
5
are true
the output M
5
is true
C
0
Logic Levels
Active HIGH
Active LOW
L
0
1
A
0
L
0
1
A
1
H
1
0
A
2
L
0
1
A
3
H
1
0
B
0
H
1
0
B
1
L
0
1
B
2
L
0
1
B
3
H
1
0
S
0
H
1
0
S
1
H
1
0
S
2
L
0
1
S
3
L
0
1
C
4
H
1
0
Active HIGH 0
a
10
a
9
e
3
a
16
Active LOW 1
a
5
a
6
e
12
a
0
FIGURE 1 Active HIGH versus Active LOW Interpretation
2
Functional Description
(Continued)
TL F 9513 – 5
FIGURE 2 3-Bit Adder
TL F 9513 – 6
FIGURE 3 2-Bit and 1-Bit Adders
TL F 9513 – 7
FIGURE 4 5-Input Encoder
TL F 9513 – 8
FIGURE 5 5-Input Majority Gate
3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
4
TL F 9513 – 9
Logic Diagram
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
65 C to
a
150 C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to V
CC
b
0 5V to
a
5 5V
twice the rated I
OL
(mA)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
b
60
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
20 mA
I
OL
e
20 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V (C
O
)
V
IN
e
0 5V (A
n
B
n
)
V
OUT
e
0V
V
O
e
HIGH
V
O
e
LOW
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
25
25
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 6
b
1 2
b
150
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
I
CCL
V
mA
mA
mA
V
mA
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
Max
36
36
55
55
5
