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SN54HCT04, SN74HCT04
HEX INVERTERS
SCLS042D – JULY 1986 – REVISED JULY 2003
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-µA Max I
CC
D
D
D
D
Typical t
pd
= 13 ns
±4-mA
Output Drive at 5 V
Low Input Current of 1
µA
Max
Inputs Are TTL-Voltage Compatible
SN54HCT04 . . . FK PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
6A
6Y
5A
5Y
4A
4Y
1Y
1A
NC
V
CC
6A
2A
NC
2Y
NC
3A
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
SN54HCT04 . . . J PACKAGE
SN74HCT04 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
6Y
NC
5A
NC
5Y
NC – No internal connection
description/ordering information
These devices contain six independent inverters. They perform the Boolean function Y = A in positive logic.
ORDERING INFORMATION
TA
PDIP – N
SOIC – D
–40°C to 85°C
40°C
SOP – NS
TSSOP – PW
CDIP – J
LCCC – FK
PACKAGE†
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
–55°C to 125°C
55°C
Tube of 25
Tube of 55
ORDERABLE
PART NUMBER
SN74HCT04N
SN74HCT04D
SN74HCT04DR
SN74HCT04DT
SN74HCT04NSR
SN74HCT04PW
SN74HCT04PWR
SN74HCT04PWT
SNJ54HCT04J
SNJ54HCT04FK
SNJ54HCT04J
SNJ54HCT04FK
HT04
HCT04
HCT04
TOP-SIDE
MARKING
SN74HCT04N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
H
L
OUTPUT
Y
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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3Y
GND
NC
4Y
4A
1
SN54HCT04, SN74HCT04
HEX INVERTERS
SCLS042D – JULY 1986 – REVISED JULY 2003
logic diagram (positive logic)
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT04
MIN
VCC
VIH
VIL
VI
VO
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition rise/fall time
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
4.5
2
0.8
0
0
VCC
VCC
500
0
0
NOM
5
MAX
5.5
SN74HCT04
MIN
4.5
2
0.8
VCC
VCC
500
NOM
5
MAX
5.5
UNIT
V
V
V
V
V
ns
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
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SN54HCT04, SN74HCT04
HEX INVERTERS
SCLS042D – JULY 1986 – REVISED JULY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
ICC
∆I
CC†
Ci
TEST CONDITIONS
VI = VIH or VIL
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
IOH = –20
µA
IOH = –4 mA
IOL = 20
µA
IOL = 4 mA
VCC
4.5
45V
45V
4.5
5.5 V
5.5 V
5.5 V
4.5 V
to 5.5 V
1.4
3
TA = 25°C
MIN
TYP
MAX
4.4
3.98
4.499
4.3
0.001
0.17
±0.1
0.1
0.26
±100
2
2.4
10
SN54HCT04
MIN
4.4
3.7
0.1
0.4
±1000
40
3
10
MAX
SN74HCT04
MIN
4.4
3.84
0.1
0.33
±1000
20
2.9
10
MAX
UNIT
V
V
nA
µA
mA
pF
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
d
tt
FROM
(INPUT)
A
TO
(OUTPUT)
Y
Y
VCC
4.5 V
5.5 V
4.5 V
5.5 V
TA = 25°C
MIN
TYP
MAX
14
13
9
8
20
18
15
14
SN54HCT04
MIN
MAX
30
27
22
20
SN74HCT04
MIN
MAX
25
23
19
17
UNIT
ns
ns
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per inverter
TEST CONDITIONS
No load
TYP
20
UNIT
pF
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3
SN54HCT04, SN74HCT04
HEX INVERTERS
SCLS042D – JULY 1986 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
In-Phase
Output
3V
Input
1.3 V
tPLH
1.3 V
10%
tPHL
Out-of-Phase
Output
90%
1.3 V
10%
tf
90%
tr
Input 1.3 V
0.3 V
2.7 V
2.7 V
3V
1.3 V
0.3 V 0 V
tf
tPLH
1.3 V
10%
90%
tr
VOH
VOL
1.3 V
0V
tPHL
90%
VOH
1.3 V
10% V
OL
tf
LOAD CIRCUIT
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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•
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